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Tue, 01 Sep 2026 10:52:49 -0700 (PDT) Received: from draig.lan ([185.124.0.156]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ce464aa70sm3655225e9.6.2026.09.01.10.52.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 10:52:49 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id E1B525F829; Tue, 01 Sep 2026 18:52:47 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Gilles Grimaud Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Peter Maydell Subject: Re: [PATCH RFC v2 01/30] target/arm: support Cortex-M0+ MPU In-Reply-To: <20260829234308.33725-2-gilles.grimaud@univ-lille.fr> (Gilles Grimaud's message of "Sun, 30 Aug 2026 01:42:35 +0200") References: <20260829234308.33725-1-gilles.grimaud@univ-lille.fr> <20260829234308.33725-2-gilles.grimaud@univ-lille.fr> User-Agent: mu4e 1.14.4-pre1; emacs 30.1 Date: Tue, 01 Sep 2026 18:52:47 +0100 Message-ID: <87wlt4uads.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Gilles Grimaud writes: > From: gilles grimaud > > Cortex-M0+ implementations may provide an Armv6 PMSA MPU with eight regio= ns. QEMU already marks M-profile CPUs as PMSA, but only exposes and allocat= es the existing region model for Armv7 CPUs. This prevents a Cortex-M0+ boa= rd from enabling its optional MPU. > Just a comment for all patches, you should ensure your editor wraps at 80 columns (72 for title) as patches are often read on terminals. It's good habit to run through checkpatch.pl to pick up the minor oft-forgotten stuff. > Use QEMU's PMSAv7 state and translation path for the compatible > Armv6-M MPU register layout. Permit CONTROL.nPRIV changes when the > optional MPU is present and clear the region state on reset. Hmm will need to think about this - the file is explicitly targeting the armv7_nvic so we might want to consider renaming if indeed special casing the differences is the right thing to do. That does make the spread of changes about both nvic and cpu hard to review. Is env->pmsav7.drbar related to env.v7m.vecbase[!attrs.secure] for example. > > Signed-off-by: gilles grimaud > --- > hw/intc/armv7m_nvic.c | 3 +++ > target/arm/cpu.c | 12 +++++++++--- > target/arm/ptw.c | 3 ++- > target/arm/tcg/m_helper.c | 10 +++++++++- > 4 files changed, 23 insertions(+), 5 deletions(-) > > diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c > index a7651f831e..3140599ac1 100644 > --- a/hw/intc/armv7m_nvic.c > +++ b/hw/intc/armv7m_nvic.c > @@ -1626,6 +1626,9 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, > break; > case 0xd08: /* Vector Table Offset. */ > cpu->env.v7m.vecbase[attrs.secure] =3D value & 0xffffff80; > + if (!arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { > + cpu->env.v7m.vecbase[!attrs.secure] =3D value & 0xffffff80; > + } > break; > case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */ > if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) =3D=3D 0x05fa) { > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 77aa78f00e..f58a1db843 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -617,7 +617,8 @@ static void arm_cpu_reset_hold(Object *obj, ResetType= type) > sizeof(*env->pmsav8.rlar[M_REG_S]) > * cpu->pmsav7_dregion); > } > - } else if (arm_feature(env, ARM_FEATURE_V7)) { > + } else if (arm_feature(env, ARM_FEATURE_V7) || > + arm_feature(env, ARM_FEATURE_M)) { > memset(env->pmsav7.drbar, 0, > sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); > memset(env->pmsav7.drsr, 0, > @@ -1656,7 +1657,11 @@ static void arm_cpu_post_init(Object *obj) > #ifndef CONFIG_USER_ONLY > if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { > qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); > - if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { > + /* > + * QEMU's PMSAv7 state also models the Armv6-M MPU register layo= ut. > + */ > + if (arm_feature(&cpu->env, ARM_FEATURE_V7) || > + arm_feature(&cpu->env, ARM_FEATURE_M)) { > qdev_property_add_static(DEVICE(obj), > &arm_cpu_pmsav7_dregion_property); > } > @@ -2332,7 +2337,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) > } >=20=20 > if (arm_feature(env, ARM_FEATURE_PMSA) && > - arm_feature(env, ARM_FEATURE_V7)) { > + (arm_feature(env, ARM_FEATURE_V7) || > + arm_feature(env, ARM_FEATURE_M))) { > uint32_t nr =3D cpu->pmsav7_dregion; >=20=20 > if (nr > 0xff) { > diff --git a/target/arm/ptw.c b/target/arm/ptw.c > index a29de0385f..b366a8d3dd 100644 > --- a/target/arm/ptw.c > +++ b/target/arm/ptw.c > @@ -3901,7 +3901,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S= 1Translate *ptw, > /* PMSAv8 */ > ret =3D get_phys_addr_pmsav8(env, ptw, address, access_type, > result, fi); > - } else if (arm_feature(env, ARM_FEATURE_V7)) { > + } else if (arm_feature(env, ARM_FEATURE_V7) || > + arm_feature(env, ARM_FEATURE_M)) { > /* PMSAv7 */ And again by definition this is PMSAv7, not v6 - you'll note we have plenty of places where we do check against ARM_FEATURE_V6 (or V6K). > ret =3D get_phys_addr_pmsav7(env, ptw, address, access_type, > result, fi); > diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c > index f4ba93b291..667b2a3cbd 100644 > --- a/target/arm/tcg/m_helper.c > +++ b/target/arm/tcg/m_helper.c > @@ -16,6 +16,7 @@ > #include "qemu/bitops.h" > #include "qemu/log.h" > #include "exec/page-protection.h" > +#include "exec/cputlb.h" > #ifdef CONFIG_TCG > #include "accel/tcg/cpu-ldst-common.h" > #include "semihosting/common-semi.h" > @@ -2775,9 +2776,16 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t ma= skreg, uint32_t val) > !arm_v7m_is_handler_mode(env))) { > write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK= ) !=3D 0); > } > - if (cur_el > 0 && arm_feature(env, ARM_FEATURE_M_MAIN)) { > + if (cur_el > 0 && (arm_feature(env, ARM_FEATURE_M_MAIN) || > + env_archcpu(env)->has_mpu)) { > + uint32_t old_control =3D env->v7m.control[env->v7m.secure]; > + > env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_= MASK; > env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_N= PRIV_MASK; > + if ((old_control ^ env->v7m.control[env->v7m.secure]) & > + R_V7M_CONTROL_NPRIV_MASK) { > + tlb_flush(env_cpu(env)); > + } > } > if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { > /* --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro