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Wed, 10 Jun 2026 05:56:08 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490dca9f4b2sm42812845e9.2.2026.06.10.05.56.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 05:56:08 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 01DDF5F833; Wed, 10 Jun 2026 13:56:06 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org Subject: Re: [PATCH 3/5] target/arm: trigger timer recalc on SCR:ECVEN change In-Reply-To: <7914fe09-fdb4-4f5b-a283-aa364d0c4525@linaro.org> (Richard Henderson's message of "Tue, 9 Jun 2026 10:46:27 -0700") References: <20260609140008.3206970-1-alex.bennee@linaro.org> <20260609140008.3206970-4-alex.bennee@linaro.org> <7914fe09-fdb4-4f5b-a283-aa364d0c4525@linaro.org> User-Agent: mu4e 1.14.1; emacs 30.1 Date: Wed, 10 Jun 2026 13:56:06 +0100 Message-ID: <87wlw6ftax.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Richard Henderson writes: > On 6/9/26 07:00, Alex Benn=C3=A9e wrote: >> Toggling the ECVEN state affects the offset calculated in >> gt_phys_raw_cnt_offset so we should trigger a re-calculation on its >> change. >> Signed-off-by: Alex Benn=C3=A9e >> --- >> target/arm/helper.c | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index 5c640853060..22f5117ee54 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -37,6 +37,9 @@ >> #include "qemu/plugin.h" >> static void switch_mode(CPUARMState *env, int mode); >> +#ifndef CONFIG_USER_ONLY >> +static void gt_recalc_timer(ARMCPU *cpu, int timeridx); >> +#endif >> int compare_u64(const void *a, const void *b) >> { >> @@ -821,6 +824,12 @@ static void scr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) >> changed =3D env->cp15.scr_el3 ^ value; >> env->cp15.scr_el3 =3D value; >> +#ifndef CONFIG_USER_ONLY >> + if (changed & SCR_ECVEN) { >> + gt_recalc_timer(cpu, GTIMER_PHYS); >> + } >> +#endif >> + >> /* >> * If SCR_EL3.{NS,NSE} changes, i.e. change of security state, >> * we must invalidate all TLBs below EL3. > > Reviewed-by: Richard Henderson > > As an aside, gt_phys_raw_cnt_offset is missing a check on EL3 > existing, before the check for ECVEn set. Not many of the references to cp15.scr_el3 seem to have those checks (although I guess that may be inferred from higher up the call chain). I can add a arm_feature(env, ARM_FEATURE_EL3) in front or maybe we want something similar to arm_is_el2_enabled? > > > r~ --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro