From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, mitulkumar.ajitkumar.golani@intel.com
Subject: Re: [PATCH] drm/i915/display: Maintain alphabetical order for HAS_AS_SDP and HAS_CMRR
Date: Tue, 11 Mar 2025 20:08:48 +0200 [thread overview]
Message-ID: <87wmcvfnin.fsf@intel.com> (raw)
In-Reply-To: <20250311135925.1523852-1-ankit.k.nautiyal@intel.com>
On Tue, 11 Mar 2025, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> Reorder the macros HAS_AS_SDP and HAS_CMRR as per alphabetical order.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_device.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 717286981687..332647c4ca81 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -142,10 +142,12 @@ struct intel_display_platforms {
> func(supports_tv);
>
> #define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
> +#define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13)
> #define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5)
Y comes before _ in asciibetical order.
BR,
Jani.
> #define HAS_BIGJOINER(__display) (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
> #define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl)
> #define HAS_CDCLK_SQUASH(__display) (DISPLAY_INFO(__display)->has_cdclk_squash)
> +#define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20)
> #define HAS_CMTG(__display) (!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13)
> #define HAS_CUR_FBC(__display) (!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13))
> #define HAS_D12_PLANE_MINIMIZATION(__display) ((__display)->platform.rocketlake || (__display)->platform.alderlake_s)
> @@ -189,8 +191,6 @@ struct intel_display_platforms {
> ((__display)->platform.dgfx && DISPLAY_VER(__display) == 14)) && \
> HAS_DSC(__display))
> #define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11)
> -#define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13)
> -#define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20)
> #define INTEL_NUM_PIPES(__display) (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
> #define I915_HAS_HOTPLUG(__display) (DISPLAY_INFO(__display)->has_hotplug)
> #define OVERLAY_NEEDS_PHYSICAL(__display) (DISPLAY_INFO(__display)->overlay_needs_physical)
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-03-11 18:08 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-11 13:59 [PATCH] drm/i915/display: Maintain alphabetical order for HAS_AS_SDP and HAS_CMRR Ankit Nautiyal
2025-03-11 17:01 ` ✓ CI.Patch_applied: success for " Patchwork
2025-03-11 17:02 ` ✓ CI.checkpatch: " Patchwork
2025-03-11 17:03 ` ✓ CI.KUnit: " Patchwork
2025-03-11 17:19 ` ✓ CI.Build: " Patchwork
2025-03-11 17:21 ` ✓ CI.Hooks: " Patchwork
2025-03-11 17:23 ` ✓ CI.checksparse: " Patchwork
2025-03-11 17:43 ` ✗ Fi.CI.SPARSE: warning " Patchwork
2025-03-11 17:45 ` ✓ Xe.CI.BAT: success " Patchwork
2025-03-11 18:08 ` Jani Nikula [this message]
2025-03-12 4:30 ` [PATCH] " Nautiyal, Ankit K
2025-03-12 11:25 ` Jani Nikula
2025-03-12 16:41 ` Lucas De Marchi
2025-03-12 17:07 ` Gustavo Sousa
2025-03-13 4:38 ` Nautiyal, Ankit K
2025-03-13 4:45 ` Lucas De Marchi
2025-03-13 5:02 ` Nautiyal, Ankit K
2025-03-13 8:44 ` Jani Nikula
2025-03-11 18:10 ` ✗ i915.CI.BAT: failure for " Patchwork
2025-03-12 9:31 ` ✗ Xe.CI.Full: " Patchwork
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