From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com
Subject: Re: [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter
Date: Mon, 21 Oct 2024 15:46:53 +0300 [thread overview]
Message-ID: <87wmi1y66a.fsf@intel.com> (raw)
In-Reply-To: <20241021123414.3993899-3-ankit.k.nautiyal@intel.com>
On Mon, 21 Oct 2024, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> At the moment dsc_split represents that dsc splitter is used or not.
> With 3 DSC engines, the splitter can split into two streams or three
> streams. Make the member dsc_split as int and set that to 2 when dsc
> splitter splits to 2 stream.
Maybe also name it accordingly? "dsc split" sounds like a boolean, not
like an int.
Moreover, when you change the meaning of a member, it's often good code
hygiene to rename the member to catch any incorrect uses and to ensure
you changed them all.
>
> v2: Avoid new enum for dsc split. (Suraj)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> .../drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 20 ++++++++++++++-----
> 5 files changed, 19 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 87a27d91d15d..553e75cf118c 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1595,7 +1595,7 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
>
> /* FIXME: split only when necessary */
> if (crtc_state->dsc.slice_count > 1)
> - crtc_state->dsc.dsc_split = true;
> + crtc_state->dsc.dsc_split = 2;
>
> /* FIXME: initialize from VBT */
> vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ef1436146325..9e2f0fd0558f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5741,7 +5741,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
>
> PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
> - PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
> + PIPE_CONF_CHECK_I(dsc.dsc_split);
> PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
>
> PIPE_CONF_CHECK_BOOL(splitter.enable);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 2bb1fa64da2f..58f510909f4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1235,7 +1235,7 @@ struct intel_crtc_state {
> /* Display Stream compression state */
> struct {
> bool compression_enable;
> - bool dsc_split;
> + int dsc_split;
> /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
> u16 compressed_bpp_x16;
> u8 slice_count;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 286b272aa98c..c1867c883b73 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2409,7 +2409,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> * then we need to use 2 VDSC instances.
> */
> if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
> - pipe_config->dsc.dsc_split = true;
> + pipe_config->dsc.dsc_split = 2;
>
> ret = intel_dp_dsc_compute_params(connector, pipe_config);
> if (ret < 0) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 40525f5c4c42..3bce13c21756 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -379,7 +379,14 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
>
> static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
> {
> - return crtc_state->dsc.dsc_split ? 2 : 1;
> + switch (crtc_state->dsc.dsc_split) {
> + case 2:
> + return 2;
> + case 0:
> + default:
> + break;
> + }
> + return 1;
Seems overly complicated.
> }
>
> int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
> @@ -976,8 +983,11 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> if (!crtc_state->dsc.compression_enable)
> goto out;
>
> - crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
> - (dss_ctl1 & JOINER_ENABLE);
> + if ((dss_ctl1 & JOINER_ENABLE) &&
> + (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE))
The extra parens are unnecessary.
> + crtc_state->dsc.dsc_split = 2;
> + else
> + crtc_state->dsc.dsc_split = 0;
>
> intel_dsc_get_pps_config(crtc_state);
> out:
> @@ -988,10 +998,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
> const struct intel_crtc_state *crtc_state)
> {
> drm_printf_indent(p, indent,
> - "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n",
> + "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %d\n",
So what does the reader think when they see "split: 1" in the logs?
Split enabled?
> FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
> crtc_state->dsc.slice_count,
> - str_yes_no(crtc_state->dsc.dsc_split));
> + crtc_state->dsc.dsc_split);
> }
>
> void intel_vdsc_state_dump(struct drm_printer *p, int indent,
--
Jani Nikula, Intel
next prev parent reply other threads:[~2024-10-21 12:47 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-21 12:33 [PATCH 00/16] Add support for 3 VDSC engines 12 slices Ankit Nautiyal
2024-10-21 12:33 ` [PATCH 01/16] drm/i915/dp: Update Comment for Valid DSC Slices per Line Ankit Nautiyal
2024-10-22 4:37 ` Kandpal, Suraj
2024-10-21 12:34 ` [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter Ankit Nautiyal
2024-10-21 12:46 ` Jani Nikula [this message]
2024-10-22 3:53 ` Nautiyal, Ankit K
2024-10-22 4:51 ` Nautiyal, Ankit K
2024-10-22 7:51 ` Jani Nikula
2024-10-22 10:04 ` Nautiyal, Ankit K
2024-10-21 12:34 ` [PATCH 03/16] drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine Ankit Nautiyal
2024-10-21 12:34 ` [PATCH 04/16] drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2 Ankit Nautiyal
2024-10-21 12:34 ` [PATCH 05/16] drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine Ankit Nautiyal
2024-10-21 12:34 ` [PATCH 06/16] drm/i915/dp: Ensure hactive is divisible by slice count Ankit Nautiyal
2024-10-21 12:34 ` [PATCH 07/16] drm/i915/dp: Enable 3 DSC engines for 12 slices Ankit Nautiyal
2024-10-21 12:34 ` [PATCH 08/16] drm/i915/display: Add macro HAS_PIXEL_REPLICATION Ankit Nautiyal
2024-10-21 12:49 ` Jani Nikula
2024-10-22 4:02 ` Nautiyal, Ankit K
2024-10-21 12:34 ` [PATCH 09/16] drm/i915/display: Add support for DSC pixel replication Ankit Nautiyal
2024-10-21 12:34 ` [PATCH 10/16] drm/i915/dp_mst: Account for pixel replication for MST overhead with DSC Ankit Nautiyal
2024-10-21 12:34 ` [PATCH 11/16] drm/i915/dp: Account for pixel replication for BW computation " Ankit Nautiyal
2024-10-21 12:34 ` [PATCH 12/16] drm/i915/display: Account for pixel replication in pipe_src Ankit Nautiyal
2024-10-21 12:34 ` [PATCH 13/16] drm/i915/dp: Enable DSC pixel replication Ankit Nautiyal
2024-10-21 12:34 ` [PATCH 14/16] drm/i915/dsc: Introduce odd pixel removal Ankit Nautiyal
2024-10-21 12:34 ` [PATCH 15/16] drm/i915/display: Adjust Pipe SRC Width for Odd Pixels Ankit Nautiyal
2024-10-21 12:34 ` [PATCH 16/16] drm/i915/dp: Add Check for Odd Pixel Requirement Ankit Nautiyal
2024-10-21 12:37 ` ✓ CI.Patch_applied: success for Add support for 3 VDSC engines 12 slices (rev4) Patchwork
2024-10-21 12:38 ` ✗ CI.checkpatch: warning " Patchwork
2024-10-21 12:39 ` ✓ CI.KUnit: success " Patchwork
2024-10-21 12:50 ` ✓ CI.Build: " Patchwork
2024-10-21 12:53 ` ✓ CI.Hooks: " Patchwork
2024-10-21 12:54 ` ✗ CI.checksparse: warning " Patchwork
2024-10-21 13:07 ` ✗ Fi.CI.CHECKPATCH: " Patchwork
2024-10-21 13:07 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-10-21 13:13 ` ✓ CI.BAT: success " Patchwork
2024-10-21 13:37 ` ✓ Fi.CI.BAT: " Patchwork
2024-10-21 15:07 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-10-21 17:44 ` ✗ CI.FULL: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2024-10-23 6:52 [PATCH 00/16] Add support for 3 VDSC engines 12 slices Ankit Nautiyal
2024-10-23 6:52 ` [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter Ankit Nautiyal
2024-10-23 8:42 ` Kandpal, Suraj
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