From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C84E5C433EF for ; Mon, 14 Mar 2022 10:00:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 424BF10E28A; Mon, 14 Mar 2022 10:00:55 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4D80010E28A for ; Mon, 14 Mar 2022 10:00:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647252054; x=1678788054; h=from:to:subject:in-reply-to:references:date:message-id: mime-version:content-transfer-encoding; bh=4oF5WJxw/tlSYMwq63QTZl//PxXo/g0vPq4j6h5A5+k=; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH v2 09/16] drm/i915: Introduce intel_panel_drrs_type() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 11 Mar 2022, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Add a helper to determine which type of DRRS the panel supports. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_drrs.c | 10 +++------- > drivers/gpu/drm/i915/display/intel_panel.c | 10 ++++++++++ > drivers/gpu/drm/i915/display/intel_panel.h | 2 ++ > 3 files changed, 15 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/= i915/display/intel_drrs.c > index 2a58bf4cb6cd..c663df51a84a 100644 > --- a/drivers/gpu/drm/i915/display/intel_drrs.c > +++ b/drivers/gpu/drm/i915/display/intel_drrs.c > @@ -48,11 +48,8 @@ > */ >=20=20 > static bool can_enable_drrs(struct intel_connector *connector, > - const struct intel_crtc_state *pipe_config, > - const struct drm_display_mode *downclock_mode) > + const struct intel_crtc_state *pipe_config) > { > - const struct drm_i915_private *i915 =3D to_i915(connector->base.dev); > - > if (pipe_config->vrr.enable) > return false; >=20=20 > @@ -65,8 +62,7 @@ static bool can_enable_drrs(struct intel_connector *con= nector, > if (pipe_config->has_psr) > return false; >=20=20 > - return downclock_mode && > - i915->vbt.drrs_type =3D=3D DRRS_TYPE_SEAMLESS; > + return intel_panel_drrs_type(connector) =3D=3D DRRS_TYPE_SEAMLESS; > } >=20=20 > void > @@ -80,7 +76,7 @@ intel_drrs_compute_config(struct intel_dp *intel_dp, > intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); > int pixel_clock; >=20=20 > - if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { > + if (!can_enable_drrs(connector, pipe_config)) { > if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) > intel_zero_m_n(&pipe_config->dp_m2_n2); > return; > diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm= /i915/display/intel_panel.c > index 3ca37766ccb3..c15f5e3d53d1 100644 > --- a/drivers/gpu/drm/i915/display/intel_panel.c > +++ b/drivers/gpu/drm/i915/display/intel_panel.c > @@ -83,6 +83,16 @@ int intel_panel_get_modes(struct intel_connector *conn= ector) > return num_modes; > } >=20=20 > +enum drrs_type intel_panel_drrs_type(struct intel_connector *connector) > +{ > + struct drm_i915_private *i915 =3D to_i915(connector->base.dev); > + > + if (!connector->panel.downclock_mode) > + return DRRS_TYPE_NONE; > + > + return i915->vbt.drrs_type; > +} > + > int intel_panel_compute_config(struct intel_connector *connector, > struct drm_display_mode *adjusted_mode) > { > diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm= /i915/display/intel_panel.h > index 88e6f5c217d8..e86100903f9e 100644 > --- a/drivers/gpu/drm/i915/display/intel_panel.h > +++ b/drivers/gpu/drm/i915/display/intel_panel.h > @@ -9,6 +9,7 @@ > #include >=20=20 > enum drm_connector_status; > +enum drrs_type; > struct drm_connector; > struct drm_connector_state; > struct drm_display_mode; > @@ -33,6 +34,7 @@ const struct drm_display_mode * > intel_panel_downclock_mode(struct intel_connector *connector, > const struct drm_display_mode *adjusted_mode); > int intel_panel_get_modes(struct intel_connector *connector); > +enum drrs_type intel_panel_drrs_type(struct intel_connector *connector); > enum drm_mode_status > intel_panel_mode_valid(struct intel_connector *connector, > const struct drm_display_mode *mode); --=20 Jani Nikula, Intel Open Source Graphics Center