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SAEximRunCond expanded to false Cc: kernel-team@android.com, kvm@vger.kernel.org, Andre Przywara , Christoffer Dall , kvmarm@lists.cs.columbia.edu, Ganapatrao Kulkarni , linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Mon, 17 Jan 2022 17:06:10 +0000, "Russell King (Oracle)" wrote: > > On Mon, Nov 29, 2021 at 08:00:49PM +0000, Marc Zyngier wrote: > > From: Christoffer Dall > > > > Reset the VCPU with PSTATE.M = EL2h when the nested virtualization > > feature is enabled on the VCPU. > > > > Signed-off-by: Christoffer Dall > > [maz: rework register reset not to use empty data structures] > > Signed-off-by: Marc Zyngier > > Reviewed-by: Russell King (Oracle) > > However, a couple of comments below. > > > --- > > arch/arm64/kvm/reset.c | 10 ++++++++-- > > 1 file changed, 8 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c > > index 426bd7fbc3fd..38a7182819fb 100644 > > --- a/arch/arm64/kvm/reset.c > > +++ b/arch/arm64/kvm/reset.c > > @@ -27,6 +27,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > /* Maximum phys_shift supported for any VM on this host */ > > @@ -38,6 +39,9 @@ static u32 kvm_ipa_limit; > > #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \ > > PSR_F_BIT | PSR_D_BIT) > > > > +#define VCPU_RESET_PSTATE_EL2 (PSR_MODE_EL2h | PSR_A_BIT | PSR_I_BIT | \ > > + PSR_F_BIT | PSR_D_BIT) > > + > > #define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \ > > PSR_AA32_I_BIT | PSR_AA32_F_BIT) > > > > @@ -176,8 +180,8 @@ static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu) > > if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is32bit) > > return false; > > > > - /* MTE is incompatible with AArch32 */ > > - if (kvm_has_mte(vcpu->kvm) && is32bit) > > + /* MTE and NV are incompatible with AArch32 */ > > + if ((kvm_has_mte(vcpu->kvm) || nested_virt_in_use(vcpu)) && is32bit) > > return false; > > It seems we have a bunch of: > > if (something && is32bit) > return false; > > tests here - would it make sense to do: > > if (is32bit) { > if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1)) > return false; > > /* MTE is incompatible with AArch32 */ > if (kvm_has_mte(vcpu->kvm)) > return false; > > /* NV is incompatible with AArch32 */ > if (nested_virt_in_use(vcpu)) > return false; > } > > in terms of improved readability? Agreed. I've now reworked to follow this pattern. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C708C433F5 for ; Thu, 27 Jan 2022 12:45:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220127_044346_898437_921AFA7A X-CRM114-Status: GOOD ( 29.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 17 Jan 2022 17:06:10 +0000, "Russell King (Oracle)" wrote: > > On Mon, Nov 29, 2021 at 08:00:49PM +0000, Marc Zyngier wrote: > > From: Christoffer Dall > > > > Reset the VCPU with PSTATE.M = EL2h when the nested virtualization > > feature is enabled on the VCPU. > > > > Signed-off-by: Christoffer Dall > > [maz: rework register reset not to use empty data structures] > > Signed-off-by: Marc Zyngier > > Reviewed-by: Russell King (Oracle) > > However, a couple of comments below. > > > --- > > arch/arm64/kvm/reset.c | 10 ++++++++-- > > 1 file changed, 8 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c > > index 426bd7fbc3fd..38a7182819fb 100644 > > --- a/arch/arm64/kvm/reset.c > > +++ b/arch/arm64/kvm/reset.c > > @@ -27,6 +27,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > /* Maximum phys_shift supported for any VM on this host */ > > @@ -38,6 +39,9 @@ static u32 kvm_ipa_limit; > > #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \ > > PSR_F_BIT | PSR_D_BIT) > > > > +#define VCPU_RESET_PSTATE_EL2 (PSR_MODE_EL2h | PSR_A_BIT | PSR_I_BIT | \ > > + PSR_F_BIT | PSR_D_BIT) > > + > > #define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \ > > PSR_AA32_I_BIT | PSR_AA32_F_BIT) > > > > @@ -176,8 +180,8 @@ static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu) > > if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is32bit) > > return false; > > > > - /* MTE is incompatible with AArch32 */ > > - if (kvm_has_mte(vcpu->kvm) && is32bit) > > + /* MTE and NV are incompatible with AArch32 */ > > + if ((kvm_has_mte(vcpu->kvm) || nested_virt_in_use(vcpu)) && is32bit) > > return false; > > It seems we have a bunch of: > > if (something && is32bit) > return false; > > tests here - would it make sense to do: > > if (is32bit) { > if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1)) > return false; > > /* MTE is incompatible with AArch32 */ > if (kvm_has_mte(vcpu->kvm)) > return false; > > /* NV is incompatible with AArch32 */ > if (nested_virt_in_use(vcpu)) > return false; > } > > in terms of improved readability? Agreed. I've now reworked to follow this pattern. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA391C433EF for ; Thu, 27 Jan 2022 12:43:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236738AbiA0Mnt (ORCPT ); Thu, 27 Jan 2022 07:43:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233016AbiA0Mns (ORCPT ); Thu, 27 Jan 2022 07:43:48 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47E6EC061747 for ; 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Thu, 27 Jan 2022 12:43:43 +0000 Date: Thu, 27 Jan 2022 12:43:43 +0000 Message-ID: <87wnil5oxs.wl-maz@kernel.org> From: Marc Zyngier To: "Russell King (Oracle)" Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Andre Przywara , Christoffer Dall , Jintack Lim , Haibo Xu , Ganapatrao Kulkarni , James Morse , Suzuki K Poulose , Alexandru Elisei , kernel-team@android.com Subject: Re: [PATCH v5 08/69] KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set In-Reply-To: References: <20211129200150.351436-1-maz@kernel.org> <20211129200150.351436-9-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux@armlinux.org.uk, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, andre.przywara@arm.com, christoffer.dall@arm.com, jintack@cs.columbia.edu, haibo.xu@linaro.org, gankulkarni@os.amperecomputing.com, james.morse@arm.com, suzuki.poulose@arm.com, alexandru.elisei@arm.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Mon, 17 Jan 2022 17:06:10 +0000, "Russell King (Oracle)" wrote: > > On Mon, Nov 29, 2021 at 08:00:49PM +0000, Marc Zyngier wrote: > > From: Christoffer Dall > > > > Reset the VCPU with PSTATE.M = EL2h when the nested virtualization > > feature is enabled on the VCPU. > > > > Signed-off-by: Christoffer Dall > > [maz: rework register reset not to use empty data structures] > > Signed-off-by: Marc Zyngier > > Reviewed-by: Russell King (Oracle) > > However, a couple of comments below. > > > --- > > arch/arm64/kvm/reset.c | 10 ++++++++-- > > 1 file changed, 8 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c > > index 426bd7fbc3fd..38a7182819fb 100644 > > --- a/arch/arm64/kvm/reset.c > > +++ b/arch/arm64/kvm/reset.c > > @@ -27,6 +27,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > /* Maximum phys_shift supported for any VM on this host */ > > @@ -38,6 +39,9 @@ static u32 kvm_ipa_limit; > > #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \ > > PSR_F_BIT | PSR_D_BIT) > > > > +#define VCPU_RESET_PSTATE_EL2 (PSR_MODE_EL2h | PSR_A_BIT | PSR_I_BIT | \ > > + PSR_F_BIT | PSR_D_BIT) > > + > > #define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \ > > PSR_AA32_I_BIT | PSR_AA32_F_BIT) > > > > @@ -176,8 +180,8 @@ static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu) > > if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is32bit) > > return false; > > > > - /* MTE is incompatible with AArch32 */ > > - if (kvm_has_mte(vcpu->kvm) && is32bit) > > + /* MTE and NV are incompatible with AArch32 */ > > + if ((kvm_has_mte(vcpu->kvm) || nested_virt_in_use(vcpu)) && is32bit) > > return false; > > It seems we have a bunch of: > > if (something && is32bit) > return false; > > tests here - would it make sense to do: > > if (is32bit) { > if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1)) > return false; > > /* MTE is incompatible with AArch32 */ > if (kvm_has_mte(vcpu->kvm)) > return false; > > /* NV is incompatible with AArch32 */ > if (nested_virt_in_use(vcpu)) > return false; > } > > in terms of improved readability? Agreed. I've now reworked to follow this pattern. Thanks, M. -- Without deviation from the norm, progress is not possible.