From: Jani Nikula <jani.nikula@linux.intel.com>
To: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Implement WM0 cursor WA for DG2
Date: Wed, 24 Nov 2021 12:23:08 +0200 [thread overview]
Message-ID: <87wnkxlunn.fsf@intel.com> (raw)
In-Reply-To: <20211118093907.18510-1-stanislav.lisovskiy@intel.com>
On Thu, 18 Nov 2021, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> Bug in the register unit which results in WM1 register
> used when only WM0 is enabled on cursor.
> Software workaround is when only WM0 enabled on cursor,
> copy contents of CUR_WM_0[30:0] (exclude the enable bit)
> into CUR_WM_1[30:0].
>
> v2: - s/dev_priv/i915/ (Ville Syrjälä)
> - Removed unneeded brackets (Ville Syrjälä)
>
> HSDES: 14012656716
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 89dc7f69baf3..01fa3fac1b57 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5095,6 +5095,18 @@ skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
> }
> }
>
> +static bool icl_need_wm1_wa(struct drm_i915_private *i915,
> + enum plane_id plane_id)
Commit subject having "WM0 cursor WA" and the function saying "wm1_wa"
looks like a discrepancy to the casual reader.
BR,
Jani.
> +{
> + /*
> + * Wa_1408961008:icl, ehl
> + * Wa_14012656716:tgl, adl
> + * Underruns with WM1+ disabled
> + */
> + return DISPLAY_VER(i915) == 11 ||
> + (IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
> +}
> +
> static int
> skl_allocate_plane_ddb(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> @@ -5265,11 +5277,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
> total[plane_id], uv_total[plane_id]);
>
> - /*
> - * Wa_1408961008:icl, ehl
> - * Underruns with WM1+ disabled
> - */
> - if (DISPLAY_VER(dev_priv) == 11 &&
> + if (icl_need_wm1_wa(dev_priv, plane_id) &&
> level == 1 && wm->wm[0].enable) {
> wm->wm[level].blocks = wm->wm[0].blocks;
> wm->wm[level].lines = wm->wm[0].lines;
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2021-11-24 10:23 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-18 9:39 [Intel-gfx] [PATCH] drm/i915/dg2: Implement WM0 cursor WA for DG2 Stanislav Lisovskiy
2021-11-18 14:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Implement WM0 cursor WA for DG2 (rev2) Patchwork
2021-11-19 2:22 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-11-24 10:23 ` Jani Nikula [this message]
2021-11-24 10:33 ` [Intel-gfx] [PATCH] drm/i915/dg2: Implement WM0 cursor WA for DG2 Lisovskiy, Stanislav
2021-11-24 10:57 ` Jani Nikula
-- strict thread matches above, loose matches on Subject: below --
2021-11-17 13:43 Stanislav Lisovskiy
2021-11-17 15:48 ` Ville Syrjälä
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