* [kvm-unit-tests PATCH] x86: tscdeadline timer testing when apic is hw disabled
@ 2020-08-03 8:01 Wanpeng Li
2020-08-03 12:41 ` Vitaly Kuznetsov
0 siblings, 1 reply; 4+ messages in thread
From: Wanpeng Li @ 2020-08-03 8:01 UTC (permalink / raw)
To: kvm
Cc: Paolo Bonzini, Sean Christopherson, Vitaly Kuznetsov, Wanpeng Li,
Jim Mattson, Joerg Roedel
From: Wanpeng Li <wanpengli@tencent.com>
This patch adds tscdeadline timer testing when apic is hw disabled.
Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
---
x86/apic.c | 27 +++++++++++++++++++++------
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/x86/apic.c b/x86/apic.c
index a7681fe..bcf56e2 100644
--- a/x86/apic.c
+++ b/x86/apic.c
@@ -30,15 +30,18 @@ static void tsc_deadline_timer_isr(isr_regs_t *regs)
eoi();
}
-static void __test_tsc_deadline_timer(void)
+static void __test_tsc_deadline_timer(bool apic_enabled)
{
handle_irq(TSC_DEADLINE_TIMER_VECTOR, tsc_deadline_timer_isr);
irq_enable();
wrmsr(MSR_IA32_TSCDEADLINE, rdmsr(MSR_IA32_TSC));
asm volatile ("nop");
- report(tdt_count == 1, "tsc deadline timer");
- report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing");
+ if (apic_enabled) {
+ report(tdt_count == 1, "tsc deadline timer");
+ report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing");
+ } else
+ report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer is not set");
}
static int enable_tsc_deadline_timer(void)
@@ -54,10 +57,10 @@ static int enable_tsc_deadline_timer(void)
}
}
-static void test_tsc_deadline_timer(void)
+static void test_tsc_deadline_timer(bool apic_enabled)
{
if(enable_tsc_deadline_timer()) {
- __test_tsc_deadline_timer();
+ __test_tsc_deadline_timer(apic_enabled);
} else {
report_skip("tsc deadline timer not detected");
}
@@ -132,6 +135,17 @@ static void verify_disabled_apic_mmio(void)
write_cr8(cr8);
}
+static void verify_disabled_apic_tsc_deadline_timer(void)
+{
+ reset_apic();
+ if (enable_tsc_deadline_timer()) {
+ disable_apic();
+ __test_tsc_deadline_timer(false);
+ } else {
+ report_skip("tsc deadline timer not detected");
+ }
+}
+
static void test_apic_disable(void)
{
volatile u32 *lvr = (volatile u32 *)(APIC_DEFAULT_PHYS_BASE + APIC_LVR);
@@ -148,6 +162,7 @@ static void test_apic_disable(void)
report(!this_cpu_has(X86_FEATURE_APIC),
"CPUID.1H:EDX.APIC[bit 9] is clear");
verify_disabled_apic_mmio();
+ verify_disabled_apic_tsc_deadline_timer();
reset_apic();
report((rdmsr(MSR_IA32_APICBASE) & (APIC_EN | APIC_EXTD)) == APIC_EN,
@@ -668,7 +683,7 @@ int main(void)
test_apic_timer_one_shot();
test_apic_change_mode();
- test_tsc_deadline_timer();
+ test_tsc_deadline_timer(true);
return report_summary();
}
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [kvm-unit-tests PATCH] x86: tscdeadline timer testing when apic is hw disabled
2020-08-03 8:01 [kvm-unit-tests PATCH] x86: tscdeadline timer testing when apic is hw disabled Wanpeng Li
@ 2020-08-03 12:41 ` Vitaly Kuznetsov
2020-08-03 12:56 ` Paolo Bonzini
0 siblings, 1 reply; 4+ messages in thread
From: Vitaly Kuznetsov @ 2020-08-03 12:41 UTC (permalink / raw)
To: Wanpeng Li, kvm
Cc: Paolo Bonzini, Sean Christopherson, Wanpeng Li, Jim Mattson,
Joerg Roedel
Wanpeng Li <kernellwp@gmail.com> writes:
> From: Wanpeng Li <wanpengli@tencent.com>
>
> This patch adds tscdeadline timer testing when apic is hw disabled.
>
> Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
> ---
> x86/apic.c | 27 +++++++++++++++++++++------
> 1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/x86/apic.c b/x86/apic.c
> index a7681fe..bcf56e2 100644
> --- a/x86/apic.c
> +++ b/x86/apic.c
> @@ -30,15 +30,18 @@ static void tsc_deadline_timer_isr(isr_regs_t *regs)
> eoi();
> }
>
> -static void __test_tsc_deadline_timer(void)
> +static void __test_tsc_deadline_timer(bool apic_enabled)
> {
> handle_irq(TSC_DEADLINE_TIMER_VECTOR, tsc_deadline_timer_isr);
> irq_enable();
>
> wrmsr(MSR_IA32_TSCDEADLINE, rdmsr(MSR_IA32_TSC));
> asm volatile ("nop");
> - report(tdt_count == 1, "tsc deadline timer");
> - report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing");
> + if (apic_enabled) {
> + report(tdt_count == 1, "tsc deadline timer");
> + report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing");
> + } else
> + report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer is not set");
I'd suggest we also check that the timer didn't fire, e.g.
report(tdt_count == 0, "tsc deadline timer didn't fire");
as a bonus, we'd get another reason to use braces for both branches of
the 'if' (which is a good thing regardless).
> }
>
> static int enable_tsc_deadline_timer(void)
> @@ -54,10 +57,10 @@ static int enable_tsc_deadline_timer(void)
> }
> }
>
> -static void test_tsc_deadline_timer(void)
> +static void test_tsc_deadline_timer(bool apic_enabled)
> {
> if(enable_tsc_deadline_timer()) {
> - __test_tsc_deadline_timer();
> + __test_tsc_deadline_timer(apic_enabled);
> } else {
> report_skip("tsc deadline timer not detected");
> }
> @@ -132,6 +135,17 @@ static void verify_disabled_apic_mmio(void)
> write_cr8(cr8);
> }
>
> +static void verify_disabled_apic_tsc_deadline_timer(void)
> +{
> + reset_apic();
> + if (enable_tsc_deadline_timer()) {
> + disable_apic();
> + __test_tsc_deadline_timer(false);
> + } else {
> + report_skip("tsc deadline timer not detected");
> + }
> +}
> +
> static void test_apic_disable(void)
> {
> volatile u32 *lvr = (volatile u32 *)(APIC_DEFAULT_PHYS_BASE + APIC_LVR);
> @@ -148,6 +162,7 @@ static void test_apic_disable(void)
> report(!this_cpu_has(X86_FEATURE_APIC),
> "CPUID.1H:EDX.APIC[bit 9] is clear");
> verify_disabled_apic_mmio();
> + verify_disabled_apic_tsc_deadline_timer();
>
> reset_apic();
> report((rdmsr(MSR_IA32_APICBASE) & (APIC_EN | APIC_EXTD)) == APIC_EN,
> @@ -668,7 +683,7 @@ int main(void)
>
> test_apic_timer_one_shot();
> test_apic_change_mode();
> - test_tsc_deadline_timer();
> + test_tsc_deadline_timer(true);
>
> return report_summary();
> }
--
Vitaly
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [kvm-unit-tests PATCH] x86: tscdeadline timer testing when apic is hw disabled
2020-08-03 12:41 ` Vitaly Kuznetsov
@ 2020-08-03 12:56 ` Paolo Bonzini
2020-08-04 7:08 ` Wanpeng Li
0 siblings, 1 reply; 4+ messages in thread
From: Paolo Bonzini @ 2020-08-03 12:56 UTC (permalink / raw)
To: Vitaly Kuznetsov, Wanpeng Li, kvm
Cc: Sean Christopherson, Wanpeng Li, Jim Mattson, Joerg Roedel
On 03/08/20 14:41, Vitaly Kuznetsov wrote:
>> - report(tdt_count == 1, "tsc deadline timer");
>> - report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing");
>> + if (apic_enabled) {
>> + report(tdt_count == 1, "tsc deadline timer");
>> + report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing");
>> + } else
>> + report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer is not set");
> I'd suggest we also check that the timer didn't fire, e.g.
>
> report(tdt_count == 0, "tsc deadline timer didn't fire");
>
> as a bonus, we'd get another reason to use braces for both branches of
> the 'if' (which is a good thing regardless).
>
Agreed, and KVM also needs to return 0 if the APIC is hardware-disabled
I think?
Paolo
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [kvm-unit-tests PATCH] x86: tscdeadline timer testing when apic is hw disabled
2020-08-03 12:56 ` Paolo Bonzini
@ 2020-08-04 7:08 ` Wanpeng Li
0 siblings, 0 replies; 4+ messages in thread
From: Wanpeng Li @ 2020-08-04 7:08 UTC (permalink / raw)
To: Paolo Bonzini
Cc: Vitaly Kuznetsov, kvm, Sean Christopherson, Wanpeng Li,
Jim Mattson, Joerg Roedel
On Mon, 3 Aug 2020 at 20:56, Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> On 03/08/20 14:41, Vitaly Kuznetsov wrote:
> >> - report(tdt_count == 1, "tsc deadline timer");
> >> - report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing");
> >> + if (apic_enabled) {
> >> + report(tdt_count == 1, "tsc deadline timer");
> >> + report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing");
> >> + } else
> >> + report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer is not set");
> > I'd suggest we also check that the timer didn't fire, e.g.
> >
> > report(tdt_count == 0, "tsc deadline timer didn't fire");
Agreed.
> >
> > as a bonus, we'd get another reason to use braces for both branches of
> > the 'if' (which is a good thing regardless).
> >
>
> Agreed, and KVM also needs to return 0 if the APIC is hardware-disabled
> I think?
Just sent out a patch to do it.
Wanpeng
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-08-04 7:08 UTC | newest]
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2020-08-03 8:01 [kvm-unit-tests PATCH] x86: tscdeadline timer testing when apic is hw disabled Wanpeng Li
2020-08-03 12:41 ` Vitaly Kuznetsov
2020-08-03 12:56 ` Paolo Bonzini
2020-08-04 7:08 ` Wanpeng Li
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