Re: [PATCH v5 08/13] drm/i915/icl: Define TA_TIMING_PARAM registers

[Jani Nikula <jani.nikula@intel.com>]

On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch defines DSI_TA_TIMING_PARAM and
> DPHY_TA_TIMING_PARAM registers used in
> dphy programming.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0dbdd57..1d13ba9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10115,6 +10115,20 @@ enum skl_power_gate {
>  #define  HS_EXIT_OVERRIDE		(1 << 7)
>  #define  HS_EXIT_TIME(x)		(x << 0)
>  
> +#define _DPHY_TA_TIMING_PARAM_0		0x162188
> +#define _DPHY_TA_TIMING_PARAM_1		0x6c188
> +#define DPHY_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
> +						   _DPHY_TA_TIMING_PARAM_0,\
> +						   _DPHY_TA_TIMING_PARAM_1)
> +#define _DSI_TA_TIMING_PARAM_0		0x6b098
> +#define _DSI_TA_TIMING_PARAM_1		0x6b898
> +#define DSI_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
> +						   _DSI_TA_TIMING_PARAM_0,\
> +						   _DSI_TA_TIMING_PARAM_1)
> +#define  TA_SURE_OVERRIDE		(1 << 31)
> +#define  TA_SURE_TIME(x)		(x << 16)
> +#define  TA_SURE_TIME_MASK		(0x1f << 16)

Please stick to _SHIFT. And in any case macro arguments need parens
around them.

Please add all the fields for the registers in one go.

BR,
Jani.


> +
>  /* bits 31:0 */
>  #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
>  #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)

-- 
Jani Nikula, Intel Open Source Graphics Center
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