Re: [PATCH 5/5] drm/i915/dp: Remove useless debug about TPS3 support

[Jani Nikula <jani.nikula@linux.intel.com>]

On Mon, 18 Sep 2017, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> We already print training pattern used during link training and also
> print if the source or sink does not support TPS3 for HBR2 link rates,
> see intel_dp_training_pattern().

Yeah, this was useful a long time ago.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>



>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 4 ----
>  1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index cc129aa444ac..2d41cd684557 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4718,10 +4718,6 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
>  	if (intel_encoder->type != INTEL_OUTPUT_EDP)
>  		intel_encoder->type = INTEL_OUTPUT_DP;
>  
> -	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
> -		      yesno(intel_dp_source_supports_hbr2(intel_dp)),
> -		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
> -
>  	if (intel_dp->reset_link_params) {
>  		/* Initial max link lane count */
>  		intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);

-- 
Jani Nikula, Intel Open Source Technology Center
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