From: Jani Nikula <jani.nikula@linux.intel.com>
To: Kenneth Graunke <kenneth@whitecape.org>,
daniel.vetter@ffwll.ch, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Add OACONTROL to the command parser register whitelist.
Date: Wed, 26 Mar 2014 11:57:55 +0200 [thread overview]
Message-ID: <87wqfhgu3g.fsf@intel.com> (raw)
In-Reply-To: <1395813123-2027-1-git-send-email-kenneth@whitecape.org>
On Wed, 26 Mar 2014, Kenneth Graunke <kenneth@whitecape.org> wrote:
> Mesa needs to be able to write OACONTROL in order to expose the
> Observability Architecture's performance counters via OpenGL.
>
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 3 insertions(+)
>
> This patch needs to go before
>
> commit 6d42f94084b8c69813d7ecd0466c33fe561bf127
> Author: Brad Volkin <bradley.d.volkin@intel.com>
> Date: Tue Feb 18 10:15:57 2014 -0800
>
> drm/i915: Enable command parsing by default
>
> in whatever branch gets submitted to Dave Airlie. Or, that commit needs
> to be reverted. Otherwise, every OpenGL program will abort. Examples
> of programs that abort include GNOME, KDE, Firefox, and glxgears.
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index bae7c2f..d4a50b9 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -415,6 +415,7 @@ static const u32 gen7_render_regs[] = {
> GEN7_SO_WRITE_OFFSET(1),
> GEN7_SO_WRITE_OFFSET(2),
> GEN7_SO_WRITE_OFFSET(3),
> + OACONTROL,
Comment above gen7_render_regs array:
* Register whitelists, sorted by increasing register offset.
You'll get a DRM_ERROR for this.
Daniel, naughty naughty for pushing this already!
BR,
Jani.
> };
>
> static const u32 gen7_blt_regs[] = {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9f9e2b7..0ebc20d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -427,6 +427,8 @@
> /* There are the 4 64-bit counter registers, one for each stream output */
> #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
>
> +#define OACONTROL 0x2360
> +
> #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
> #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
> #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
> --
> 1.9.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
next prev parent reply other threads:[~2014-03-26 9:57 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-26 5:52 [PATCH] drm/i915: Add OACONTROL to the command parser register whitelist Kenneth Graunke
2014-03-26 6:21 ` Daniel Vetter
2014-03-26 16:03 ` Volkin, Bradley D
2014-03-26 16:38 ` Daniel Vetter
2014-03-26 17:37 ` Kenneth Graunke
2014-03-26 18:26 ` Volkin, Bradley D
2014-03-26 21:48 ` Daniel Vetter
2014-03-26 22:34 ` Kenneth Graunke
2014-03-27 7:57 ` Daniel Vetter
2014-03-27 15:57 ` Volkin, Bradley D
2014-03-27 20:16 ` Daniel Vetter
2014-03-27 21:34 ` Kenneth Graunke
2014-03-27 22:44 ` Daniel Vetter
2014-03-27 23:22 ` Kenneth Graunke
2014-05-16 19:05 ` Jesse Barnes
2014-05-16 19:20 ` Chris Wilson
2014-05-16 19:34 ` Jesse Barnes
2014-05-16 19:49 ` Chris Wilson
2014-05-16 20:12 ` Jesse Barnes
2014-05-16 19:53 ` Jesse Barnes
2014-05-16 20:12 ` Volkin, Bradley D
2014-05-16 20:14 ` Jesse Barnes
2014-03-27 23:42 ` Volkin, Bradley D
2014-03-28 7:36 ` Chris Wilson
2014-03-26 9:57 ` Jani Nikula [this message]
2014-03-26 10:41 ` [PATCH v2] " Kenneth Graunke
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