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Thu, 20 Aug 2026 11:30:08 +0000 Date: Thu, 20 Aug 2026 12:32:39 +0100 Message-ID: <87y0e1ni20.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Leonardo Bras , Catalin Marinas , Will Deacon , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton , Peter Maydell , Yao Yuan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v19 04/14] KVM: arm64: Ensure GCS memory effects are visible In-Reply-To: <3cc4cccd-1a4a-487e-8ac6-9bbbc9713e58@sirena.org.uk> References: <20260812-arm64-gcs-v19-0-9105afd828ac@kernel.org> <20260812-arm64-gcs-v19-4-9105afd828ac@kernel.org> <3cc4cccd-1a4a-487e-8ac6-9bbbc9713e58@sirena.org.uk> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: broonie@kernel.org, leo.bras@arm.com, catalin.marinas@arm.com, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, shuah@kernel.org, tabba@google.com, oupton@kernel.org, peter.maydell@linaro.org, yaoyuan@linux.alibaba.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 19 Aug 2026 19:08:01 +0100, Mark Brown wrote: >=20 > On Wed, Aug 19, 2026 at 06:23:11PM +0100, Leonardo Bras wrote: >=20 > > You state that we do _not_ use GCS in the hypervisor, nor in the host. > > I understand that we GCSB() when we exit the vcpu context, but why woul= d we=20 > > need to GCSB() before getting back in? >=20 > > If cpus will GCSB() on guest_exit, and host/hyp does not use GCS, there= =20 > > should be no GCS pending operation at the entry point. >=20 > That's there to ensure that updates written by another PE are seen, > following the same pattern as DDI0487 M.c K10.6.5 example K10-8 (or the > prior migration between PEs example, that has barriers due to the stack > switch operations rather than as distinct instructions). This makes no sense at all. The guest itself is in charge of its own coherency. =46rom the PoV of the hypervisor, this only needs to be guaranteed when a vcpu is migrated from one physical CPU to another, as this is invisible to the guest. Given that this can only happen on in the interval between vcpu_put() and vcpu_load(), the sole location where this could make any sense is at vcpu_put() time. And even that can be relaxed in the NV case, where we transition between ELs rather than CPUs. Hammering things in the run loop is both expensive and pointless. M. --=20 Jazz isn't dead. It just smells funny.