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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Richard Weinberger <richard@nod.at>,
	 Vignesh Raghavendra <vigneshr@ti.com>,
	 Pratyush Yadav <pratyush@kernel.org>,
	 Michael Walle <michael@walle.cc>,
	 linux-mtd@lists.infradead.org,
	 Jakub Czapiga <czapiga@google.com>,
	 Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Takahiro Kuwano <takahiro.kuwano@infineon.com>
Subject: Re: [PATCH 1/2] mtd: spi-nor: Fix RDCR controller capability core check
Date: Tue, 17 Mar 2026 10:20:50 +0100	[thread overview]
Message-ID: <87y0jqerrh.fsf@bootlin.com> (raw)
In-Reply-To: <acc9c661-d102-4302-a276-fd8de20562db@linaro.org> (Tudor Ambarus's message of "Tue, 10 Mar 2026 11:24:56 +0200")

Hello,

>>> These will always fail because there
>>> is now an inconsistency: the address cycles are forced to 4 (then 3)
>>> bytes, but the bus width during the address cycles rightfully remains 0:
>>> impossible, the operation is invalid.
>
> I like Cheng's details on how it's failing. Would you please add what he
> detailed there?
> ```
> This modified operation is then rejected by spi_mem_check_op() in the
> core spi-mem.c because it has a non-zero address length but a zero address
> buswidth, which is an invalid combination.
> ```

I've added the precision about the invalid combination of non-zero
address length and zero bus width. I feel like it's a repetition of my
previous sentence, but I'm fine with it if it clarifies.

Thanks!
Miquèl

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  parent reply	other threads:[~2026-03-17  9:21 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-08 12:14 [PATCH 1/2] mtd: spi-nor: Fix RDCR controller capability core check Miquel Raynal
2026-01-08 12:14 ` [PATCH 2/2] mtd: spi-nor: Rename spi_nor_spimem_check_op() Miquel Raynal
2026-03-10  9:54   ` Tudor Ambarus
2026-03-17  9:33     ` Miquel Raynal
2026-03-17 11:39       ` Tudor Ambarus
2026-03-17 13:18         ` Miquel Raynal
2026-03-09 14:55 ` [PATCH 1/2] mtd: spi-nor: Fix RDCR controller capability core check Miquel Raynal
2026-03-10  9:24   ` Tudor Ambarus
2026-03-10  9:38     ` Tudor Ambarus
2026-03-17  9:21       ` Miquel Raynal
2026-03-17  9:20     ` Miquel Raynal [this message]
2026-03-17  9:25       ` Tudor Ambarus
2026-03-11  7:02   ` Takahiro.Kuwano
2026-03-13 11:10   ` Pratyush Yadav
2026-03-13 14:34     ` Miquel Raynal
2026-03-13 16:42       ` Pratyush Yadav

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