Re: [PATCH v3 0/2] tests/qtest: Add RISC-V IOMMU bare-metal test using iommu-testdev

[Fabiano Rosas <farosas@suse.de>]

chao.liu.zevorn@gmail.com writes:

> From: Chao Liu <chao.liu.zevorn@gmail.com>
>
> Hi,
>
> This patch series adds a bare-metal qtest for the RISC-V IOMMU using the
> iommu-testdev framework. The test exercises address translation paths
> without requiring a full guest OS boot.
>
> Motivation
> ----------
>
> The existing RISC-V IOMMU qtest (riscv-iommu-test.c) focuses on PCI device
> enumeration and register-level validation:
> - PCI configuration space verification (vendor/device ID)
> - Register reset value checks
> - Queue initialization procedures (CQ/FQ/PQ)
>
> However, it does not test the actual address translation functionality.
> This new test fills that gap by using iommu-testdev to trigger DMA
> transactions and validate the IOMMU's translation logic.
>
> Comparison with Existing Test
> -----------------------------
>
> | Feature               | riscv-iommu-test.c | iommu-riscv-test.c (new) |
> |-----------------------|--------------------|--------------------------|
> | PCI config            | Yes                | No                       |
> | Register reset        | Yes                | No                       |
> | Queue init            | Yes                | Yes (via helper)         |
> | Bare translation      | No                 | Yes                      |
> | S-stage (SV39)        | No                 | Yes                      |
> | G-stage (SV39x4)      | No                 | Yes                      |
> | Nested translation    | No                 | Yes                      |
> | DMA verification      | No                 | Yes                      |
> | Uses iommu-testdev    | No                 | Yes                      |
>
> The new test provides:
> - Device context (DC) configuration and validation
> - SV39 page table walks for S-stage translation
> - SV39x4 page table walks for G-stage translation
> - Nested translation combining both stages
> - FCTL register constraint validation
> - End-to-end DMA verification
>
> Note: The current implementation only supports SV39/SV39x4. Support for
> SV48/SV48x4/SV57/SV57x4 can be added in future patches.
>
> Testing
> -------
>
> QTEST_QEMU_BINARY=./build/qemu-system-riscv64 \
>   ./build/tests/qtest/iommu-riscv-test --tap -k
>
> Changes v2 -> v3
> ----------------
> - Removed duplicate header includes in both patches (Tao)
> - Fixed memory leak of state->iommu_dev and state->testdev in
>   riscv_iommu_test_setup() in patch 2 (Fabiano)
>
> Changes v1 -> v2
> ----------------
> - Removed unused 'mode' parameter from qriommu_get_pte_attrs() function
> - Simplified PTE mask definitions in header file by using direct hex
>   values instead of individual bit defines (removed QRIOMMU_PTE_V/R/W/X
>   /U/G/A/D macros), added comment referencing target/riscv/cpu_bits.h
> - Cleaned up variable declarations in qriommu_setup_translation_tables()
>   to follow C99 style (declare at point of use)
> - Minor code style improvements
>
> Thanks,
> Chao
>
> Chao Liu (2):
>   tests/qtest/libqos: Add RISC-V IOMMU helper library
>   tests/qtest: Add RISC-V IOMMU bare-metal test
>
>  MAINTAINERS                          |   2 +
>  tests/qtest/iommu-riscv-test.c       | 279 +++++++++++++++++++
>  tests/qtest/libqos/meson.build       |   2 +-
>  tests/qtest/libqos/qos-riscv-iommu.c | 403 +++++++++++++++++++++++++++
>  tests/qtest/libqos/qos-riscv-iommu.h | 164 +++++++++++
>  tests/qtest/meson.build              |   5 +-
>  6 files changed, 853 insertions(+), 2 deletions(-)
>  create mode 100644 tests/qtest/iommu-riscv-test.c
>  create mode 100644 tests/qtest/libqos/qos-riscv-iommu.c
>  create mode 100644 tests/qtest/libqos/qos-riscv-iommu.h

I'm queuing this, but if riscv folks want to pull it, it's fine as well.