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Fri, 22 Aug 2025 12:26:15 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 33a5c3fa-7f53-11f0-a32b-13f23c93f187 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=sgEra1dfrSTYaJ7OqnnSBuoMbHZcSZcf3m06fpK9ugTG+zttYvHXgO1YDdzuQAXkt8dGAV7HA5dW2PYx1LkPXIoXZXalkGlhQSSRvzMig4Tjc0+VwWuFYy3mryAxGbai6qbWwrKIvMBJUDsnLG7sQo2kBAqjhaR/bV9DoXZ1BrRjnk8SrG26oYBdAsLClimrYKEwIj/BSOybaJ5z5TAzq2dpRS/5nhg+mokjqfTksLzfyo9lDdKp0XYs1OZcgjA1qHi7fwRxZ4R4iMlzaz0ZdKzK84Lv0xOOmE+ewP49tQyIY7JxjrDdvGQcWSlN99rixeRKXzaBHlWLzdg0kuWDCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV1PR03MB10456.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 79395254-7794-44da-694a-08dde177168c X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Aug 2025 12:26:15.2101 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3e5HjebRLhVj5LsSsPHunZ3DcA48t1GrMRofLMaxkECV0RjPXnaG1+aJlU5DHFhUA1lAyGKc+Mm8/Sd5ucxIKWkWlCrNATAGw9BujWB8B5c= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR03MB7165 Hi Leonid, Leonid Komarianskyi writes: > Hi Volodymyr, > > On 21.08.25 19:46, Volodymyr Babchuk wrote: >>=20 >>=20 >>=20 >> Leonid Komarianskyi writes: >>=20 >>> The Dom0 configuration logic in create_dom0() has been updated >>> to account for extended SPIs when supported by the hardware and >>> enabled with CONFIG_GICV3_ESPI. These changes ensure the proper >>> calculation of the maximum number of SPIs and eSPIs available for Dom0. >>> >>> When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is >>> enabled, the maximum number of eSPI interrupts is calculated using >>> the ESPI_BASE_INTID offset (4096) and limited at 1024, with 32 IRQs >>> subtracted. To ensure compatibility with non-Dom0 domains, this >>> adjustment is applied by the toolstack during domain creation, while >>> for Dom0 it is handled directly during VGIC initialization. If eSPIs >>> are not supported, the calculation defaults to using the standard SPI >>> range, with a maximum value of 992 interrupt lines as it works now. >>> >>> Signed-off-by: Leonid Komarianskyi >>> >>> --- >>> Changes in V2: >>> - no changes >>> --- >>> xen/arch/arm/domain_build.c | 10 ++++++++++ >>> xen/arch/arm/include/asm/vgic.h | 11 +++++++++++ >>> 2 files changed, 21 insertions(+) >>> >>> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c >>> index d91a71acfd..fa5abf2dfb 100644 >>> --- a/xen/arch/arm/domain_build.c >>> +++ b/xen/arch/arm/domain_build.c >>> @@ -2055,6 +2055,16 @@ void __init create_dom0(void) >>> /* The vGIC for DOM0 is exactly emulating the hardware GIC */ >>> dom0_cfg.arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE; >>> dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_SPIS; >>> +#ifdef CONFIG_GICV3_ESPI >>> + /* >>> + * Check if the hardware supports extended SPIs (even if the appro= priate config is set). >>> + * If not, the common SPI range will be used. Otherwise overwrite = the nr_spis with the >>> + * maximum available INTID from eSPI range. In that case, the numb= er of regular SPIs will >>> + * be adjusted to the maximum value during vGIC initialization. >>> + */ >>> + if ( gic_number_espis() > 0 ) >>> + dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_ESPIS; >>> +#endif >>> dom0_cfg.arch.tee_type =3D tee_get_type(); >>> dom0_cfg.max_vcpus =3D dom0_max_vcpus(); >>> =20 >>> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm= /vgic.h >>> index 9fa4523018..117b3aa92c 100644 >>> --- a/xen/arch/arm/include/asm/vgic.h >>> +++ b/xen/arch/arm/include/asm/vgic.h >>> @@ -353,6 +353,17 @@ extern void vgic_check_inflight_irqs_pending(struc= t vcpu *v, >>> /* Default number of vGIC SPIs. 32 are substracted to cover local IRQ= s. */ >>> #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32= ) >>> =20 >>> +#ifdef CONFIG_GICV3_ESPI >>> +/* >>> + * Returns the maximum eSPI INTID subtracted by 32. For non-Dom0 domai= ns, the >>> + * toolstack applies the same adjustment to cover local IRQs. We will = add back >>> + * this value during VGIC initialization. This ensures consistent hand= ling for Dom0 >>> + * and other domains. For the regular SPI range interrupts in this cas= e, the maximum >>> + * value of VGIC_DEF_NR_SPIS will be used. >>> + */ >>> +#define VGIC_DEF_NR_ESPIS (ESPI_BASE_INTID + min(gic_number_espis(), 1= 024U) - 32) >> Name of the define is wrong, as it is not number of eSPIs. Actually, thi= s is >> maximum SPI (including eSPIs) number. > > > Thank you for your review. > Would it be okay if I rename this macro to VGIC_DEF_MAX_SPI? Yes, I think this is better name. --=20 WBR, Volodymyr=