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Thu, 16 Jan 2025 07:09:20 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5db73642379sm61663a12.8.2025.01.16.07.09.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jan 2025 07:09:19 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id CC0D860812; Thu, 16 Jan 2025 15:09:18 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Peter Maydell Cc: Ilya Leoshkevich , Richard Henderson , Paolo Bonzini , qemu-devel@nongnu.org, Nina Schoetterl-Glausch Subject: Re: [PATCH] accel/tcg: Call tcg_tb_insert() for one-insn TBs In-Reply-To: (Peter Maydell's message of "Thu, 16 Jan 2025 12:24:53 +0000") References: <20250115232022.27332-1-iii@linux.ibm.com> <87frljhvzk.fsf@draig.linaro.org> <65e146746377bc307affc627f47c4700aaaac4ba.camel@linux.ibm.com> User-Agent: mu4e 1.12.8; emacs 29.4 Date: Thu, 16 Jan 2025 15:09:18 +0000 Message-ID: <87y0zahk2p.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Peter Maydell writes: > On Thu, 16 Jan 2025 at 11:48, Ilya Leoshkevich wrote: >> >> On Thu, 2025-01-16 at 11:06 +0000, Peter Maydell wrote: >> > The original reported problem here seems to me like it's a >> > problem with whatever target's frontend code this is. >> > This is a single instruction TB, so either: >> > * the generated code for it completes the insn without >> > raising an exception (no problem) >> > * the generated code for it should raise an exception >> > without having modified the CPU state (so there would >> > be nothing to do for restore_state_to_opc) >> > >> > It sounds like the target is generating code which does >> > something like: >> > * do part of the instruction, including updating some of >> > the CPU state >> > * then decide it needs to raise an exception, and rely on >> > the restore_state_to_opc handling to undo the state updates >> > it did previously >> > >> > The assumption of the "throwaway single insn TB" is that >> > you don't do that (i.e. that restore_state_to_opc is only >> > there for the benefit of multi-insn TBs). > >> The problem is not a partial state update in an instruction, but rather >> that on some targets restore_state_to_opc is more than just a >> "restore" - it is also "prepare for handling an exception", i.e.: >> >> - arm: exception.syndrome >> - hppa: unwind_breg, psw_n >> - mips: btarget >> - openrisc: ppc >> - riscv: excp_uw2 >> - s390x: int_pgm_ilen >> >> Some of these may be wrong due to unfamiliarity with the respective >> architectures, sorry - but this illustrates the idea. > > Ah, yes, thanks for the clear explanation. The "throw away > the TB" design didn't consider that (or vice-versa). We can certainly do with better docstrings for tcg_tb_lookup (via the region tree) and tb_lookup (using cache and/or QHT) to make it clear the difference between the two. I don't think we should ever use tcg_tb_lookup for the purposes of executing a TB, just for resolution. We have a few spare CF_ flags so maybe we could have a CF_RUNONCE flag which is set for these TBs and assert its not set in tb_lookup along with the current CF_INVALID flag. We could possibly set CF_INVALID before executing the TB as we don't check the tb state from tb_gen_code() before executing it but I guess that might be a little too magic. Rich, WDYT? > > thanks > -- PMM --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro