All of lore.kernel.org
 help / color / mirror / Atom feed
From: Thomas Gleixner <tglx@linutronix.de>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Florian Fainelli <florian.fainelli@broadcom.com>,
	Broadcom internal kernel review list
	<bcm-kernel-feedback-list@broadcom.com>,
	Huacai Chen <chenhuacai@kernel.org>,
	Serge Semin <fancer.lancer@gmail.com>,
	Paul Burton <paulburton@kernel.org>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
	Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: Re: [PATCH v3 09/10] irqchip: irq-mips-cpu: Rework software IRQ handling flow
Date: Fri, 23 Aug 2024 21:37:09 +0200	[thread overview]
Message-ID: <87y14nf2u2.ffs@tglx> (raw)
In-Reply-To: <20240810-b4-mips-ipi-improvements-v3-9-1224fd7c4096@flygoat.com>

On Sat, Aug 10 2024 at 13:39, Jiaxun Yang wrote:

Please fix the subsystem prefix.

> Remove unnecessary irq_chip hooks for software interrupts,
> and don't mask them in ack hook to match kernel's expectation
> on handling flow.

What's that expectation? You fail to explain why the current code is not
matching them.

> Create a irq_chip for regular (non-MT) mode software interrupts
> so they will be acked as well.

I'm failing to understand what this is about due to the lack of
information above.

> -static struct irq_chip mips_cpu_irq_controller = {
> +static unsigned int mips_sw_irq_startup(struct irq_data *d)
> +{
> +	clear_c0_cause(C_SW0 << d->hwirq);
> +	back_to_back_c0_hazard();
> +	unmask_mips_irq(d);
> +	return 0;
> +}
> +
> +static void mips_sw_irq_ack(struct irq_data *d)
> +{
> +	clear_c0_cause(C_SW0 << d->hwirq);
> +	back_to_back_c0_hazard();
> +}

Please move these functions to the place which actually requires them,
i.e. after the cpu controller struct and before the new one.

> +
> +static const struct irq_chip mips_cpu_irq_controller = {
>  	.name		= "MIPS",
>  	.irq_ack	= mask_mips_irq,
>  	.irq_mask	= mask_mips_irq,
> @@ -60,11 +74,19 @@ static struct irq_chip mips_cpu_irq_controller = {
>  	.irq_enable	= unmask_mips_irq,
>  };
>  
> +static const struct irq_chip mips_cpu_sw_irq_controller = {
> +	.name		= "MIPS",
> +	.irq_startup	= mips_sw_irq_startup,
> +	.irq_ack	= mips_sw_irq_ack,
> +	.irq_mask	= mask_mips_irq,
> +	.irq_unmask	= unmask_mips_irq,
> +};

  
>  asmlinkage void __weak plat_irq_dispatch(void)
>  {
> @@ -152,11 +170,14 @@ asmlinkage void __weak plat_irq_dispatch(void)
>  static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
>  			     irq_hw_number_t hw)
>  {
> -	struct irq_chip *chip;
> +	const struct irq_chip *chip;
>  
> -	if (hw < 2 && cpu_has_mipsmt) {
> -		/* Software interrupts are used for MT/CMT IPI */
> -		chip = &mips_mt_cpu_irq_controller;
> +	if (hw < 2) {
> +		chip = &mips_cpu_sw_irq_controller;
> +#ifdef CONFIG_MIPS_MT
> +		if (cpu_has_mipsmt)
> +			chip = &mips_mt_cpu_irq_controller;
> +#endif

Please move this into a helper function:

#ifdef CONFIG_MIPS_MT
static inline const struct irq_chip *mips_get_cpu_irqchip(void)
{
        return cpu_has_mipsmt ? &mips_mt_cpu_sw_irq_controller : &mips_cpu_sw_irq_controller;
}
#else
#define 
static inline const struct irq_chip *mips_get_cpu_irqchip(void)
{
        return &mips_cpu_sw_irq_controller;
}
#endif

Hmm?

Thanks,

        tglx

  reply	other threads:[~2024-08-23 19:37 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-10 12:39 [PATCH v3 00/10] MIPS: IPI Improvements Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 01/10] MIPS: smp: Make IPI interrupts scalable Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 02/10] MIPS: smp: Manage IPI interrupts as percpu_devid interrupts Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 03/10] MIPS: smp: Provide platform IPI virq & domain hooks Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 04/10] MIPS: Move mips_smp_ipi_init call after prepare_cpus Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 05/10] MIPS: smp: Implement IPI stats Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 06/10] irqchip: irq-mips-gic: Switch to ipi_mux Jiaxun Yang
2024-08-23 19:27   ` Thomas Gleixner
2024-08-10 12:39 ` [PATCH v3 07/10] MIPS: Implement get_mips_sw_int hook Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 08/10] MIPS: GIC: Implement get_sw_int hook Jiaxun Yang
2024-08-10 12:39 ` [PATCH v3 09/10] irqchip: irq-mips-cpu: Rework software IRQ handling flow Jiaxun Yang
2024-08-23 19:37   ` Thomas Gleixner [this message]
2024-08-24  9:52     ` Jiaxun Yang
2024-08-25  0:17       ` Thomas Gleixner
2024-08-10 12:39 ` [PATCH v3 10/10] MIPS: smp-mt: Rework IPI functions Jiaxun Yang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87y14nf2u2.ffs@tglx \
    --to=tglx@linutronix.de \
    --cc=bcm-kernel-feedback-list@broadcom.com \
    --cc=chenhuacai@kernel.org \
    --cc=fancer.lancer@gmail.com \
    --cc=florian.fainelli@broadcom.com \
    --cc=jiaxun.yang@flygoat.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mips@vger.kernel.org \
    --cc=paulburton@kernel.org \
    --cc=tsbogend@alpha.franken.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.