From: Thomas Gleixner <tglx@linutronix.de>
To: Huacai Chen <chenhuacai@loongson.cn>
Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org,
Xuefeng Li <lixuefeng@loongson.cn>,
Huacai Chen <chenhuacai@gmail.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhuacai@loongson.cn>,
stable@vger.kernel.org, Tianli Xiong <xiongtianli@loongson.cn>
Subject: Re: [PATCH] irqchip/loongson-liointc: Set different ISRs for different cores
Date: Fri, 21 Jun 2024 20:40:17 +0200 [thread overview]
Message-ID: <87y16ym966.ffs@tglx> (raw)
In-Reply-To: <20240612070106.2060334-1-chenhuacai@loongson.cn>
On Wed, Jun 12 2024 at 15:01, Huacai Chen wrote:
> In the liointc hardware, there are different ISRs for different cores.
I have no idea what ISR means in that context. Can you please spell it
out with proper words so that people not familiar with the details can
understand it?
> We always use core#0's ISR before but has no problem, it is because the
> interrupts are routed to core#0 by default. If we change the routing,
> we should set correct ISRs for different cores.
We do nothing. The code does.
See https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#changelog
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Tianli Xiong <xiongtianli@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This Signed-off-by chain is wrong. If Tianli is the author then this
needs a From: Tianli in the changelog. If you developed it together then
this lacks a Co-developed-by tag.
See Documentation/process/
Thanks,
tglx
next prev parent reply other threads:[~2024-06-21 18:40 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-12 7:01 [PATCH] irqchip/loongson-liointc: Set different ISRs for different cores Huacai Chen
2024-06-21 18:40 ` Thomas Gleixner [this message]
2024-06-22 2:25 ` Huacai Chen
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