From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0524FC433EF for ; Wed, 20 Jul 2022 03:03:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238707AbiGTDDa (ORCPT ); Tue, 19 Jul 2022 23:03:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239226AbiGTDD1 (ORCPT ); Tue, 19 Jul 2022 23:03:27 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CCFF1BEAB; Tue, 19 Jul 2022 20:03:25 -0700 (PDT) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LngWD5dzkz4x7X; Wed, 20 Jul 2022 13:03:20 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ellerman.id.au; s=201909; t=1658286203; bh=07a5cjF0e9SE4ghrWPN59Y1xcS8Op+XIj+zd97Y/sD4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=VBUywPF7BJl/iHXB6z0aZcik5dkO6ISMryTwHHBOfdsHO/F7DusRlENuecPpb0ocU h0aptq1KpohsSf3IbkKyI8f/yuYSR1zSllHmHraP+a2MZhaIo0+7L6e50EE+01F76G phcNILJZ/UkLOwibUep6WX+/H3wRxrGPwmLv8gGFpgLZV+3zJCq9ePTtD4Z+2l0JX6 qTSYLwY1fVjmsG5ebVAceqlzLnx4mIDtEmy+qrMvPYMF6f58UUhgep38kjZhOXRySi 5zet7uxpBCKVR+InMq55C9PgjnZUsRY+/vkd5H1wFqmQ6FjMy34sVQ45g1LvS6H0Ty Ff7032tCwAY/Q== From: Michael Ellerman To: Gabriel Paubert Cc: "Jason A. Donenfeld" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, x86@kernel.org, Catalin Marinas , Heiko Carstens , Johannes Berg , Harald Freudenberger , "H . Peter Anvin" , Alexander Gordeev , Borislav Petkov , Will Deacon , Thomas Gleixner Subject: Re: [PATCH v2] random: handle archrandom in plural words In-Reply-To: References: <20220717200356.75060-1-Jason@zx2c4.com> <87a697dj9s.fsf@mpe.ellerman.id.au> Date: Wed, 20 Jul 2022 13:03:19 +1000 Message-ID: <87y1wocwp4.fsf@mpe.ellerman.id.au> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-s390@vger.kernel.org Gabriel Paubert writes: > On Mon, Jul 18, 2022 at 04:31:11PM +1000, Michael Ellerman wrote: >> "Jason A. Donenfeld" writes: >> > The archrandom interface was originally designed for x86, which supplies >> > RDRAND/RDSEED for receiving random words into registers, resulting in >> > one function to generate an int and another to generate a long. However, >> > other architectures don't follow this. >> > >> > On arm64, the SMCCC TRNG interface can return between 1 and 3 words. On >> > s390, the CPACF TRNG interface can return between 1 and 32 words for the >> > same cost as for one word. On UML, the os_getrandom() interface can return >> > arbitrary amounts. >> > >> > So change the api signature to take a "words" parameter designating the >> > maximum number of words requested, and then return the number of words >> > generated. >> >> On powerpc a word is 32-bits and a doubleword is 64-bits (at least >> according to the ISA). I think that's also true on other 64-bit >> architectures. > > IIRC, this is (or was) not the case on Alpha, where word was defined as > 16 bits. All assembly mnemonics had w for 16 bits, l for 32 bits, and q > for 64 bits. Yeah I should have said on *some* other 64-bit arches. Seems to be a common feature/hack on arches that have evolved over time, or been inspired by earlier arches. The latest Power ISA has octwords :) cheers From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A17BC433EF for ; Wed, 20 Jul 2022 03:04:04 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4LngX22jpPz3bqx for ; Wed, 20 Jul 2022 13:04:02 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ellerman.id.au header.i=@ellerman.id.au header.a=rsa-sha256 header.s=201909 header.b=VBUywPF7; dkim-atps=neutral Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4LngWJ3vlFz2xkg for ; Wed, 20 Jul 2022 13:03:24 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ellerman.id.au header.i=@ellerman.id.au header.a=rsa-sha256 header.s=201909 header.b=VBUywPF7; dkim-atps=neutral Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LngWD5dzkz4x7X; Wed, 20 Jul 2022 13:03:20 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ellerman.id.au; s=201909; t=1658286203; bh=07a5cjF0e9SE4ghrWPN59Y1xcS8Op+XIj+zd97Y/sD4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=VBUywPF7BJl/iHXB6z0aZcik5dkO6ISMryTwHHBOfdsHO/F7DusRlENuecPpb0ocU h0aptq1KpohsSf3IbkKyI8f/yuYSR1zSllHmHraP+a2MZhaIo0+7L6e50EE+01F76G phcNILJZ/UkLOwibUep6WX+/H3wRxrGPwmLv8gGFpgLZV+3zJCq9ePTtD4Z+2l0JX6 qTSYLwY1fVjmsG5ebVAceqlzLnx4mIDtEmy+qrMvPYMF6f58UUhgep38kjZhOXRySi 5zet7uxpBCKVR+InMq55C9PgjnZUsRY+/vkd5H1wFqmQ6FjMy34sVQ45g1LvS6H0Ty Ff7032tCwAY/Q== From: Michael Ellerman To: Gabriel Paubert Subject: Re: [PATCH v2] random: handle archrandom in plural words In-Reply-To: References: <20220717200356.75060-1-Jason@zx2c4.com> <87a697dj9s.fsf@mpe.ellerman.id.au> Date: Wed, 20 Jul 2022 13:03:19 +1000 Message-ID: <87y1wocwp4.fsf@mpe.ellerman.id.au> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-s390@vger.kernel.org, "Jason A. Donenfeld" , Thomas Gleixner , Will Deacon , Catalin Marinas , Heiko Carstens , x86@kernel.org, linux-kernel@vger.kernel.org, Harald Freudenberger , "H . Peter Anvin" , Johannes Berg , Borislav Petkov , linuxppc-dev@lists.ozlabs.org, Alexander Gordeev , linux-arm-kernel@lists.infradead.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Gabriel Paubert writes: > On Mon, Jul 18, 2022 at 04:31:11PM +1000, Michael Ellerman wrote: >> "Jason A. Donenfeld" writes: >> > The archrandom interface was originally designed for x86, which supplies >> > RDRAND/RDSEED for receiving random words into registers, resulting in >> > one function to generate an int and another to generate a long. However, >> > other architectures don't follow this. >> > >> > On arm64, the SMCCC TRNG interface can return between 1 and 3 words. On >> > s390, the CPACF TRNG interface can return between 1 and 32 words for the >> > same cost as for one word. On UML, the os_getrandom() interface can return >> > arbitrary amounts. >> > >> > So change the api signature to take a "words" parameter designating the >> > maximum number of words requested, and then return the number of words >> > generated. >> >> On powerpc a word is 32-bits and a doubleword is 64-bits (at least >> according to the ISA). I think that's also true on other 64-bit >> architectures. > > IIRC, this is (or was) not the case on Alpha, where word was defined as > 16 bits. All assembly mnemonics had w for 16 bits, l for 32 bits, and q > for 64 bits. Yeah I should have said on *some* other 64-bit arches. Seems to be a common feature/hack on arches that have evolved over time, or been inspired by earlier arches. The latest Power ISA has octwords :) cheers From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3814C433EF for ; Wed, 20 Jul 2022 03:04:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:References :In-Reply-To:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Sa3qVzhZPAEIwJqfc5E97kEAdvi4tnstA9awJfB4bQk=; b=KyXiyginmtlMP+ CMxVww+5LS2wX4tcmN7Hy5iPqoDi1wQrzOhCGrNmICtU2dOAkLvWXrSptwIE6B4DXLU459C7lBHh1 S8A2AkXdKQag/umY1AKqkt6vwahGiFG9TvX3QSIP5f7sh/bv5YjZ5yDiZAGtolo4qL/fuM6C0zWrK 56aZ2NPZuHAiqnB0a+bzZSIQSEy5nGfzWFt3FbnpPV/OXqJIfuQ3MUlBnfKcH8iXQD2WH4j9aV0ne MiAl/omzHPmhLtcJzQAFeydR2G1ZiZe/wtCdGPVaEk481woSFvxvtCrYIyV1bPKnL/aRuFibmrv6o n2cS2Iy+nT4UVMPM6Rcg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oDzzw-00HDZd-6B; Wed, 20 Jul 2022 03:03:40 +0000 Received: from gandalf.ozlabs.org ([150.107.74.76]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oDzzs-00HDUw-V3 for linux-arm-kernel@lists.infradead.org; Wed, 20 Jul 2022 03:03:38 +0000 Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LngWD5dzkz4x7X; Wed, 20 Jul 2022 13:03:20 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ellerman.id.au; s=201909; t=1658286203; bh=07a5cjF0e9SE4ghrWPN59Y1xcS8Op+XIj+zd97Y/sD4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=VBUywPF7BJl/iHXB6z0aZcik5dkO6ISMryTwHHBOfdsHO/F7DusRlENuecPpb0ocU h0aptq1KpohsSf3IbkKyI8f/yuYSR1zSllHmHraP+a2MZhaIo0+7L6e50EE+01F76G phcNILJZ/UkLOwibUep6WX+/H3wRxrGPwmLv8gGFpgLZV+3zJCq9ePTtD4Z+2l0JX6 qTSYLwY1fVjmsG5ebVAceqlzLnx4mIDtEmy+qrMvPYMF6f58UUhgep38kjZhOXRySi 5zet7uxpBCKVR+InMq55C9PgjnZUsRY+/vkd5H1wFqmQ6FjMy34sVQ45g1LvS6H0Ty Ff7032tCwAY/Q== From: Michael Ellerman To: Gabriel Paubert Cc: "Jason A. Donenfeld" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, x86@kernel.org, Catalin Marinas , Heiko Carstens , Johannes Berg , Harald Freudenberger , "H . Peter Anvin" , Alexander Gordeev , Borislav Petkov , Will Deacon , Thomas Gleixner Subject: Re: [PATCH v2] random: handle archrandom in plural words In-Reply-To: References: <20220717200356.75060-1-Jason@zx2c4.com> <87a697dj9s.fsf@mpe.ellerman.id.au> Date: Wed, 20 Jul 2022 13:03:19 +1000 Message-ID: <87y1wocwp4.fsf@mpe.ellerman.id.au> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220719_200337_180374_F3B0A655 X-CRM114-Status: GOOD ( 14.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Gabriel Paubert writes: > On Mon, Jul 18, 2022 at 04:31:11PM +1000, Michael Ellerman wrote: >> "Jason A. Donenfeld" writes: >> > The archrandom interface was originally designed for x86, which supplies >> > RDRAND/RDSEED for receiving random words into registers, resulting in >> > one function to generate an int and another to generate a long. However, >> > other architectures don't follow this. >> > >> > On arm64, the SMCCC TRNG interface can return between 1 and 3 words. On >> > s390, the CPACF TRNG interface can return between 1 and 32 words for the >> > same cost as for one word. On UML, the os_getrandom() interface can return >> > arbitrary amounts. >> > >> > So change the api signature to take a "words" parameter designating the >> > maximum number of words requested, and then return the number of words >> > generated. >> >> On powerpc a word is 32-bits and a doubleword is 64-bits (at least >> according to the ISA). I think that's also true on other 64-bit >> architectures. > > IIRC, this is (or was) not the case on Alpha, where word was defined as > 16 bits. All assembly mnemonics had w for 16 bits, l for 32 bits, and q > for 64 bits. Yeah I should have said on *some* other 64-bit arches. Seems to be a common feature/hack on arches that have evolved over time, or been inspired by earlier arches. The latest Power ISA has octwords :) cheers _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel