From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: Re: [PATCH 5/7] drm/i915: Take forcewake for setting the RPS thresholds Date: Mon, 20 Feb 2017 16:34:43 +0200 Message-ID: <87y3x1c4n0.fsf@gaia.fi.intel.com> References: <20170220094713.22874-1-chris@chris-wilson.co.uk> <20170220094713.22874-5-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id ADCC86E40B for ; Mon, 20 Feb 2017 14:35:54 +0000 (UTC) In-Reply-To: <20170220094713.22874-5-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org 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X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlz dApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0 b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com ([134.134.136.100]:61885 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753074AbdBTOi7 (ORCPT ); Mon, 20 Feb 2017 09:38:59 -0500 From: Mika Kuoppala To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: Chris Wilson , stable@vger.kernel.org Subject: Re: [PATCH 5/7] drm/i915: Take forcewake for setting the RPS thresholds In-Reply-To: <20170220094713.22874-5-chris@chris-wilson.co.uk> References: <20170220094713.22874-1-chris@chris-wilson.co.uk> <20170220094713.22874-5-chris@chris-wilson.co.uk> Date: Mon, 20 Feb 2017 16:34:43 +0200 Message-ID: <87y3x1c4n0.fsf@gaia.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: Chris Wilson writes: > Take forcewake for the entire duration of reprogramming the RPS > thresholds. By itself it should not achieve much as instead of going > into the FIFO, we force the device to wake for the reprograming, but it > should help in regards to the next patch that introduces a read. > > Signed-off-by: Chris Wilson The recommendation is to keep it during init. And this is part of our init and reinit to different values, this makes a lot of sense. This kind of approach was tried to byt hangs and had a significant change to the repeability. But that test didnt have rps off during reinit and the forcewake was not as exclusive as this version. Reviewed-by: Mika Kuoppala > Cc: Mika Kuoppala > Cc: stable@vger.kernel.org > --- > drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++++++------------------ > 1 file changed, 25 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index a40ad32d76eb..3041cd4988a6 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4869,25 +4869,31 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) > break; > } > > - I915_WRITE(GEN6_RP_UP_EI, > - GT_INTERVAL_FROM_US(dev_priv, ei_up)); > - I915_WRITE(GEN6_RP_UP_THRESHOLD, > - GT_INTERVAL_FROM_US(dev_priv, > - ei_up * threshold_up / 100)); > - > - I915_WRITE(GEN6_RP_DOWN_EI, > - GT_INTERVAL_FROM_US(dev_priv, ei_down)); > - I915_WRITE(GEN6_RP_DOWN_THRESHOLD, > - GT_INTERVAL_FROM_US(dev_priv, > - ei_down * threshold_down / 100)); > - > - I915_WRITE(GEN6_RP_CONTROL, > - GEN6_RP_MEDIA_TURBO | > - GEN6_RP_MEDIA_HW_NORMAL_MODE | > - GEN6_RP_MEDIA_IS_GFX | > - GEN6_RP_ENABLE | > - GEN6_RP_UP_BUSY_AVG | > - GEN6_RP_DOWN_IDLE_AVG); > + spin_lock_irq(&dev_priv->uncore.lock); > + intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); > + > + I915_WRITE_FW(GEN6_RP_UP_EI, > + GT_INTERVAL_FROM_US(dev_priv, ei_up)); > + I915_WRITE_FW(GEN6_RP_UP_THRESHOLD, > + GT_INTERVAL_FROM_US(dev_priv, > + ei_up * threshold_up / 100)); > + > + I915_WRITE_FW(GEN6_RP_DOWN_EI, > + GT_INTERVAL_FROM_US(dev_priv, ei_down)); > + I915_WRITE_FW(GEN6_RP_DOWN_THRESHOLD, > + GT_INTERVAL_FROM_US(dev_priv, > + ei_down * threshold_down / 100)); > + > + I915_WRITE_FW(GEN6_RP_CONTROL, > + GEN6_RP_MEDIA_TURBO | > + GEN6_RP_MEDIA_HW_NORMAL_MODE | > + GEN6_RP_MEDIA_IS_GFX | > + GEN6_RP_ENABLE | > + GEN6_RP_UP_BUSY_AVG | > + GEN6_RP_DOWN_IDLE_AVG); > + > + intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); > + spin_unlock_irq(&dev_priv->uncore.lock); > > dev_priv->rps.power = new_power; > dev_priv->rps.up_threshold = threshold_up; > -- > 2.11.0