From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH] drm/i915: disable PSR by default on HSW/BDW Date: Wed, 14 Dec 2016 13:58:52 +0200 Message-ID: <87y3zirabn.fsf@intel.com> References: <1481662664-18986-1-git-send-email-paulo.r.zanoni@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id B80BA6E756 for ; Wed, 14 Dec 2016 11:58:55 +0000 (UTC) In-Reply-To: <1481662664-18986-1-git-send-email-paulo.r.zanoni@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni , stable@vger.kernel.org, Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org T24gVHVlLCAxMyBEZWMgMjAxNiwgUGF1bG8gWmFub25pIDxwYXVsby5yLnphbm9uaUBpbnRlbC5j b20+IHdyb3RlOgo+IFdlJ3ZlIGJlZW4gaWdub3JpbmcgdGhlIHBvb3IgYnVnemlsbGEgcmVwb3J0 ZXJzIHRoYXQgc2F5IFBTUiBjYXVzZXMKPiBzeXN0ZW0gbG9ja3VwcyBhbmQgYWxsIG90aGVyIHNv cnRzIG9mIHByb2JsZW1zLiBUaGUgZWFybGllc3QgYnVnCj4gcmVwb3J0IGlzIGZyb20gQXByaWws IHNvIEkgdGhpbmsgd2UgY2FuIHVzZSB0aGUgInJldmVydCB0aGUgb2ZmZW5kaW5nCj4gY29tbWl0 IGlmIG5vIGZpeGVzIGFyZSBwcmVzZW50ZWQgd2l0aGluIDggbW9udGhzIiBydWxlIGhlcmUuCgpV Z2guIFNob3VsZCBiZSBtb3JlIGxpa2UgMiB3ZWVrcyBvciBzby4gV2Ugc3Vjay4gOigKCkFja2Vk LWJ5OiBKYW5pIE5pa3VsYSA8amFuaS5uaWt1bGFAaW50ZWwuY29tPgoKUFMuIFlvdSdyZSB1c2lu ZyBhIHZlcnNpb24gb2YgZ2l0IHRoYXQgc2NyZXdzIHVwICMgY29tbWVudHMgYXQgdGhlIGVuZApv ZiBDYzogbGluZXMsIHNvIEkgcHJlc3VtZSB0aGlzIGRpZG4ndCBtYWtlIGl0IHRvIHN0YWJsZSBs aXN0LiBJdCdzCmVub3VnaCB0byBoYXZlIHRoZSBDYzogaW4gdGhlIGNvbW1pdCB3aGVuIGl0IGdl dHMgYXBwbGllZCB0aG91Z2guCgo+Cj4gRml4ZXM6IDliNThlMzUyYjQ2MyAoImRybS9pOTE1OiBF bmFibGUgUFNSIGJ5IGRlZmF1bHQgb24gSGFzd2VsbCBhbmQgQnJvYWR3ZWxsLiIpCj4gQnVnemls bGE6IGh0dHBzOi8vYnVncy5mcmVlZGVza3RvcC5vcmcvc2hvd19idWcuY2dpP2lkPTk3NjAyCj4g QnVnemlsbGE6IGh0dHBzOi8vYnVncy5mcmVlZGVza3RvcC5vcmcvc2hvd19idWcuY2dpP2lkPTk3 NTE1Cj4gQnVnemlsbGE6IGh0dHBzOi8vYnVncy5mcmVlZGVza3RvcC5vcmcvc2hvd19idWcuY2dp P2lkPTk2NzM2Cj4gQnVnemlsbGE6IGh0dHBzOi8vYnVncy5mcmVlZGVza3RvcC5vcmcvc2hvd19i dWcuY2dpP2lkPTk2NzA0Cj4gQnVnemlsbGE6IGh0dHBzOi8vYnVncy5mcmVlZGVza3RvcC5vcmcv c2hvd19idWcuY2dpP2lkPTk2NTY5Cj4gQnVnemlsbGE6IGh0dHBzOi8vYnVncy5mcmVlZGVza3Rv cC5vcmcvc2hvd19idWcuY2dpP2lkPTk1MTc2Cj4gQnVnemlsbGE6IGh0dHBzOi8vYnVncy5mcmVl ZGVza3RvcC5vcmcvc2hvd19idWcuY2dpP2lkPTk0OTg1Cj4gQ2M6IDxzdGFibGVAdmdlci5rZXJu ZWwub3JnPiAjIHY0LjYrCj4gQ2M6IFJvZHJpZ28gVml2aSA8cm9kcmlnby52aXZpQGludGVsLmNv bT4KPiBDYzogSmltIEJyaWRlIDxqaW0uYnJpZGVAbGludXguaW50ZWwuY29tPgo+IFNpZ25lZC1v ZmYtYnk6IFBhdWxvIFphbm9uaSA8cGF1bG8uci56YW5vbmlAaW50ZWwuY29tPgo+IC0tLQo+ICBk cml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wc3IuYyB8IDEwICsrKy0tLS0tLS0KPiAgMSBmaWxl IGNoYW5nZWQsIDMgaW5zZXJ0aW9ucygrKSwgNyBkZWxldGlvbnMoLSkKPgo+IGRpZmYgLS1naXQg YS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wc3IuYyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2ludGVsX3Bzci5jCj4gaW5kZXggZDVmOGQwMy4uNmFjYThmZiAxMDA2NDQKPiAtLS0gYS9kcml2 ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wc3IuYwo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2ludGVsX3Bzci5jCj4gQEAgLTgyMywxMyArODIzLDkgQEAgdm9pZCBpbnRlbF9wc3JfaW5pdChz dHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYpCj4gIAlkZXZfcHJpdi0+cHNyX21taW9f YmFzZSA9IElTX0hBU1dFTEwoZGV2X3ByaXYpID8KPiAgCQlIU1dfRURQX1BTUl9CQVNFIDogQkRX X0VEUF9QU1JfQkFTRTsKPiAgCj4gLQkvKiBQZXIgcGxhdGZvcm0gZGVmYXVsdCAqLwo+IC0JaWYg KGk5MTUuZW5hYmxlX3BzciA9PSAtMSkgewo+IC0JCWlmIChJU19IQVNXRUxMKGRldl9wcml2KSB8 fCBJU19CUk9BRFdFTEwoZGV2X3ByaXYpKQo+IC0JCQlpOTE1LmVuYWJsZV9wc3IgPSAxOwo+IC0J CWVsc2UKPiAtCQkJaTkxNS5lbmFibGVfcHNyID0gMDsKPiAtCX0KPiArCS8qIFBlciBwbGF0Zm9y bSBkZWZhdWx0OiBhbGwgZGlzYWJsZWQuICovCj4gKwlpZiAoaTkxNS5lbmFibGVfcHNyID09IC0x KQo+ICsJCWk5MTUuZW5hYmxlX3BzciA9IDA7Cj4gIAo+ICAJLyogU2V0IGxpbmtfc3RhbmRieSB4 IGxpbmtfb2ZmIGRlZmF1bHRzICovCj4gIAlpZiAoSVNfSEFTV0VMTChkZXZfcHJpdikgfHwgSVNf QlJPQURXRUxMKGRldl9wcml2KSkKCi0tIApKYW5pIE5pa3VsYSwgSW50ZWwgT3BlbiBTb3VyY2Ug VGVjaG5vbG9neSBDZW50ZXIKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0 b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50 ZWwtZ2Z4Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com ([134.134.136.31]:27393 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754583AbcLNL7V (ORCPT ); Wed, 14 Dec 2016 06:59:21 -0500 From: Jani Nikula To: Paulo Zanoni , intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org, Paulo Zanoni , Rodrigo Vivi Subject: Re: [Intel-gfx] [PATCH] drm/i915: disable PSR by default on HSW/BDW In-Reply-To: <1481662664-18986-1-git-send-email-paulo.r.zanoni@intel.com> References: <1481662664-18986-1-git-send-email-paulo.r.zanoni@intel.com> Date: Wed, 14 Dec 2016 13:58:52 +0200 Message-ID: <87y3zirabn.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: On Tue, 13 Dec 2016, Paulo Zanoni wrote: > We've been ignoring the poor bugzilla reporters that say PSR causes > system lockups and all other sorts of problems. The earliest bug > report is from April, so I think we can use the "revert the offending > commit if no fixes are presented within 8 months" rule here. Ugh. Should be more like 2 weeks or so. We suck. :( Acked-by: Jani Nikula PS. You're using a version of git that screws up # comments at the end of Cc: lines, so I presume this didn't make it to stable list. It's enough to have the Cc: in the commit when it gets applied though. > > Fixes: 9b58e352b463 ("drm/i915: Enable PSR by default on Haswell and Broadwell.") > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97602 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97515 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96736 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96704 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96569 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95176 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94985 > Cc: # v4.6+ > Cc: Rodrigo Vivi > Cc: Jim Bride > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_psr.c | 10 +++------- > 1 file changed, 3 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index d5f8d03..6aca8ff 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -823,13 +823,9 @@ void intel_psr_init(struct drm_i915_private *dev_priv) > dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ? > HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE; > > - /* Per platform default */ > - if (i915.enable_psr == -1) { > - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > - i915.enable_psr = 1; > - else > - i915.enable_psr = 0; > - } > + /* Per platform default: all disabled. */ > + if (i915.enable_psr == -1) > + i915.enable_psr = 0; > > /* Set link_standby x link_off defaults */ > if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) -- Jani Nikula, Intel Open Source Technology Center