diff for duplicates of <87y5e31jem.fsf@linux.vnet.ibm.com> diff --git a/a/1.txt b/N1/1.txt index c5793f2..861f89e 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -2,14 +2,13 @@ Paul Mackerras <paulus@samba.org> writes: > On Tue, Feb 26, 2013 at 01:34:59PM +0530, Aneesh Kumar K.V wrote: >> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> ->>=20 +>> >> We look at both the segment base page size and actual page size and store >> the pte-lp-encodings in an array per base page size. ->>=20 +>> >> We also update all relevant functions to take actual page size argument >> so that we can use the correct PTE LP encoding in HPTE. This should also ->> get the basic Multiple Page Size per Segment (MPSS) support. This is nee= -ded +>> get the basic Multiple Page Size per Segment (MPSS) support. This is needed >> to enable THP on ppc64. > > Mostly looks OK, comments below... @@ -31,17 +30,16 @@ Fixed. >> index 71d0c90..48f6d99 100644 >> --- a/arch/powerpc/kvm/book3s_hv.c >> +++ b/arch/powerpc/kvm/book3s_hv.c ->> @@ -1515,7 +1515,7 @@ static void kvmppc_add_seg_page_size(struct kvm_pp= -c_one_seg_page_size **sps, ->> (*sps)->page_shift =3D def->shift; ->> (*sps)->slb_enc =3D def->sllp; ->> (*sps)->enc[0].page_shift =3D def->shift; ->> - (*sps)->enc[0].pte_enc =3D def->penc; ->> + (*sps)->enc[0].pte_enc =3D def->penc[linux_psize]; +>> @@ -1515,7 +1515,7 @@ static void kvmppc_add_seg_page_size(struct kvm_ppc_one_seg_page_size **sps, +>> (*sps)->page_shift = def->shift; +>> (*sps)->slb_enc = def->sllp; +>> (*sps)->enc[0].page_shift = def->shift; +>> - (*sps)->enc[0].pte_enc = def->penc; +>> + (*sps)->enc[0].pte_enc = def->penc[linux_psize]; >> (*sps)++; >> } > -> This will only return the entries where actual page size =3D=3D base page +> This will only return the entries where actual page size == base page > size, which basically means that KVM guests won't be able to use > MPSS. We will need to return multiple entries in that case. @@ -56,20 +54,20 @@ KVM_PPC_GET_SMMU_INFO ioct >> + unsigned int mask; >> + int i, penc, shift; >> + /* Look at the 8 bit LP value */ ->> + unsigned int lp =3D (hptep->r >> LP_SHIFT) & ((1 << LP_BITS) - 1); +>> + unsigned int lp = (hptep->r >> LP_SHIFT) & ((1 << LP_BITS) - 1); >> + ->> + penc =3D 0; ->> + for (i =3D 0; i < MMU_PAGE_COUNT; i++) { +>> + penc = 0; +>> + for (i = 0; i < MMU_PAGE_COUNT; i++) { >> + /* valid entries have a shift value */ >> + if (!mmu_psize_defs[i].shift) >> + continue; >> + >> + /* encoding bits per actual page size */ ->> + shift =3D mmu_psize_defs[i].shift - 11; +>> + shift = mmu_psize_defs[i].shift - 11; >> + if (shift > 9) ->> + shift =3D 9; ->> + mask =3D (1 << shift) - 1; ->> + if ((lp & mask) =3D=3D mmu_psize_defs[psize].penc[i]) +>> + shift = 9; +>> + mask = (1 << shift) - 1; +>> + if ((lp & mask) == mmu_psize_defs[psize].penc[i]) >> + return i; >> + } >> + return -1; @@ -81,9 +79,9 @@ KVM_PPC_GET_SMMU_INFO ioct > not the base page size. That 11 should be 12.That depends on the fact that we have below mapping - rrrr rrrz =E2=89=A58KB + rrrr rrrz ≥8KB -Yes, that 9 should be LP_BITs.=20 +Yes, that 9 should be LP_BITs. We are generating mask based on actual page size above (variable i in the for loop). @@ -104,24 +102,23 @@ will do. >> + int *psize, int *apsize, int *ssize, unsigned long *vpn) >> { >> unsigned long avpn, pteg, vpi; ->> unsigned long hpte_r =3D hpte->r; ->> unsigned long hpte_v =3D hpte->v; +>> unsigned long hpte_r = hpte->r; +>> unsigned long hpte_v = hpte->v; >> unsigned long vsid, seg_off; >> - int i, size, shift, penc; ->> + int i, size, a_size =3D MMU_PAGE_4K, shift, penc; ->>=20=20 +>> + int i, size, a_size = MMU_PAGE_4K, shift, penc; +>> >> if (!(hpte_v & HPTE_V_LARGE)) ->> size =3D MMU_PAGE_4K; ->> @@ -395,12 +422,13 @@ static void hpte_decode(struct hash_pte *hpte, uns= -igned long slot, +>> size = MMU_PAGE_4K; +>> @@ -395,12 +422,13 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot, >> /* valid entries have a shift value */ >> if (!mmu_psize_defs[size].shift) >> continue; >> - ->> - if (penc =3D=3D mmu_psize_defs[size].penc) +>> - if (penc == mmu_psize_defs[size].penc) >> - break; ->> + for (a_size =3D 0; a_size < MMU_PAGE_COUNT; a_size++) ->> + if (penc =3D=3D mmu_psize_defs[size].penc[a_size]) +>> + for (a_size = 0; a_size < MMU_PAGE_COUNT; a_size++) +>> + if (penc == mmu_psize_defs[size].penc[a_size]) >> + goto out; > > Once again I don't think this is correct, since the number of bits in @@ -140,96 +137,95 @@ But that will also need fixing as you suggested above. >> static int __init htab_dt_scan_page_sizes(unsigned long node, >> const char *uname, int depth, >> void *data) ->> @@ -294,60 +318,57 @@ static int __init htab_dt_scan_page_sizes(unsigned= - long node, ->> size /=3D 4; ->> cur_cpu_spec->mmu_features &=3D ~(MMU_FTR_16M_PAGE); +>> @@ -294,60 +318,57 @@ static int __init htab_dt_scan_page_sizes(unsigned long node, +>> size /= 4; +>> cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); >> while(size > 0) { ->> - unsigned int shift =3D prop[0]; ->> + unsigned int base_shift =3D prop[0]; ->> unsigned int slbenc =3D prop[1]; ->> unsigned int lpnum =3D prop[2]; ->> - unsigned int lpenc =3D 0; +>> - unsigned int shift = prop[0]; +>> + unsigned int base_shift = prop[0]; +>> unsigned int slbenc = prop[1]; +>> unsigned int lpnum = prop[2]; +>> - unsigned int lpenc = 0; >> struct mmu_psize_def *def; ->> - int idx =3D -1; +>> - int idx = -1; >> + int idx, base_idx; ->>=20=20 ->> size -=3D 3; prop +=3D 3; +>> +>> size -= 3; prop += 3; >> - while(size > 0 && lpnum) { ->> - if (prop[0] =3D=3D shift) ->> - lpenc =3D prop[1]; ->> + base_idx =3D get_idx_from_shift(base_shift); +>> - if (prop[0] == shift) +>> - lpenc = prop[1]; +>> + base_idx = get_idx_from_shift(base_shift); >> + if (base_idx < 0) { >> + /* >> + * skip the pte encoding also >> + */ ->> prop +=3D 2; size -=3D 2; +>> prop += 2; size -= 2; >> - lpnum--; >> + continue; >> } >> - switch(shift) { >> - case 0xc: ->> - idx =3D MMU_PAGE_4K; +>> - idx = MMU_PAGE_4K; >> - break; >> - case 0x10: ->> - idx =3D MMU_PAGE_64K; +>> - idx = MMU_PAGE_64K; >> - break; >> - case 0x14: ->> - idx =3D MMU_PAGE_1M; +>> - idx = MMU_PAGE_1M; >> - break; >> - case 0x18: ->> - idx =3D MMU_PAGE_16M; ->> + def =3D &mmu_psize_defs[base_idx]; ->> + if (base_idx =3D=3D MMU_PAGE_16M) ->> cur_cpu_spec->mmu_features |=3D MMU_FTR_16M_PAGE; +>> - idx = MMU_PAGE_16M; +>> + def = &mmu_psize_defs[base_idx]; +>> + if (base_idx == MMU_PAGE_16M) +>> cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; >> - break; >> - case 0x22: ->> - idx =3D MMU_PAGE_16G; +>> - idx = MMU_PAGE_16G; >> - break; >> - } >> - if (idx < 0) >> - continue; ->> - def =3D &mmu_psize_defs[idx]; ->> - def->shift =3D shift; ->> - if (shift <=3D 23) +>> - def = &mmu_psize_defs[idx]; +>> - def->shift = shift; +>> - if (shift <= 23) >> + ->> + def->shift =3D base_shift; ->> + if (base_shift <=3D 23) ->> def->avpnm =3D 0; +>> + def->shift = base_shift; +>> + if (base_shift <= 23) +>> def->avpnm = 0; >> else ->> - def->avpnm =3D (1 << (shift - 23)) - 1; ->> + def->avpnm =3D (1 << (base_shift - 23)) - 1; ->> def->sllp =3D slbenc; ->> - def->penc =3D lpenc; +>> - def->avpnm = (1 << (shift - 23)) - 1; +>> + def->avpnm = (1 << (base_shift - 23)) - 1; +>> def->sllp = slbenc; +>> - def->penc = lpenc; >> - /* We don't know for sure what's up with tlbiel, so >> + /* >> + * We don't know for sure what's up with tlbiel, so >> * for now we only set it for 4K and 64K pages >> */ ->> - if (idx =3D=3D MMU_PAGE_4K || idx =3D=3D MMU_PAGE_64K) ->> + if (base_idx =3D=3D MMU_PAGE_4K || base_idx =3D=3D MMU_PAGE_64K) ->> def->tlbiel =3D 1; +>> - if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K) +>> + if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) +>> def->tlbiel = 1; >> else ->> def->tlbiel =3D 0; ->>=20=20 ->> - DBG(" %d: shift=3D%02x, sllp=3D%04lx, avpnm=3D%08lx, " ->> - "tlbiel=3D%d, penc=3D%d\n", +>> def->tlbiel = 0; +>> +>> - DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, " +>> - "tlbiel=%d, penc=%d\n", >> - idx, shift, def->sllp, def->avpnm, def->tlbiel, >> - def->penc); >> + while (size > 0 && lpnum) { ->> + unsigned int shift =3D prop[0]; ->> + unsigned int penc =3D prop[1]; +>> + unsigned int shift = prop[0]; +>> + unsigned int penc = prop[1]; >> + ->> + prop +=3D 2; size -=3D 2; +>> + prop += 2; size -= 2; >> + lpnum--; >> + ->> + idx =3D get_idx_from_shift(shift); +>> + idx = get_idx_from_shift(shift); >> + if (idx < 0) >> + continue; >> + ->> + def->penc[idx] =3D penc; ->> + DBG(" %d: shift=3D%02x, sllp=3D%04lx, " ->> + "avpnm=3D%08lx, tlbiel=3D%d, penc=3D%d\n", +>> + def->penc[idx] = penc; +>> + DBG(" %d: shift=%02x, sllp=%04lx, " +>> + "avpnm=%08lx, tlbiel=%d, penc=%d\n", >> + idx, shift, def->sllp, def->avpnm, >> + def->tlbiel, def->penc[idx]); >> + } @@ -241,13 +237,18 @@ We do the below --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c -@@ -125,7 +125,7 @@ static struct mmu_psize_def mmu_psize_defaults_old[] = -=3D { - [MMU_PAGE_4K] =3D { - .shift =3D 12, - .sllp =3D 0, -- .penc =3D 0, -+ .penc =3D { [0 ... MMU_PAGE_COUNT - 1] =3D -1 }, - .avpnm =3D 0, +@@ -125,7 +125,7 @@ static struct mmu_psize_def mmu_psize_defaults_old[] = { + [MMU_PAGE_4K] = { + .shift = 12, + .sllp = 0, +- .penc = 0, ++ .penc = { [0 ... MMU_PAGE_COUNT - 1] = -1 }, + .avpnm = 0, -aneesh + +-- +To unsubscribe, send a message with 'unsubscribe linux-mm' in +the body to majordomo@kvack.org. For more info on Linux MM, +see: http://www.linux-mm.org/ . +Don't email: <a href=mailto:"dont@kvack.org"> email@kvack.org </a> diff --git a/a/content_digest b/N1/content_digest index 07fa7e3..3cdd3ef 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -5,7 +5,8 @@ "Subject\0Re: [PATCH -V1 09/24] powerpc: Decode the pte-lp-encoding bits correctly.\0" "Date\0Mon, 04 Mar 2013 17:11:53 +0530\0" "To\0Paul Mackerras <paulus@samba.org>\0" - "Cc\0linuxppc-dev@lists.ozlabs.org" + "Cc\0benh@kernel.crashing.org" + linuxppc-dev@lists.ozlabs.org " linux-mm@kvack.org\0" "\00:1\0" "b\0" @@ -13,14 +14,13 @@ "\n" "> On Tue, Feb 26, 2013 at 01:34:59PM +0530, Aneesh Kumar K.V wrote:\n" ">> From: \"Aneesh Kumar K.V\" <aneesh.kumar@linux.vnet.ibm.com>\n" - ">>=20\n" + ">> \n" ">> We look at both the segment base page size and actual page size and store\n" ">> the pte-lp-encodings in an array per base page size.\n" - ">>=20\n" + ">> \n" ">> We also update all relevant functions to take actual page size argument\n" ">> so that we can use the correct PTE LP encoding in HPTE. This should also\n" - ">> get the basic Multiple Page Size per Segment (MPSS) support. This is nee=\n" - "ded\n" + ">> get the basic Multiple Page Size per Segment (MPSS) support. This is needed\n" ">> to enable THP on ppc64.\n" ">\n" "> Mostly looks OK, comments below...\n" @@ -42,17 +42,16 @@ ">> index 71d0c90..48f6d99 100644\n" ">> --- a/arch/powerpc/kvm/book3s_hv.c\n" ">> +++ b/arch/powerpc/kvm/book3s_hv.c\n" - ">> @@ -1515,7 +1515,7 @@ static void kvmppc_add_seg_page_size(struct kvm_pp=\n" - "c_one_seg_page_size **sps,\n" - ">> \t(*sps)->page_shift =3D def->shift;\n" - ">> \t(*sps)->slb_enc =3D def->sllp;\n" - ">> \t(*sps)->enc[0].page_shift =3D def->shift;\n" - ">> -\t(*sps)->enc[0].pte_enc =3D def->penc;\n" - ">> +\t(*sps)->enc[0].pte_enc =3D def->penc[linux_psize];\n" + ">> @@ -1515,7 +1515,7 @@ static void kvmppc_add_seg_page_size(struct kvm_ppc_one_seg_page_size **sps,\n" + ">> \t(*sps)->page_shift = def->shift;\n" + ">> \t(*sps)->slb_enc = def->sllp;\n" + ">> \t(*sps)->enc[0].page_shift = def->shift;\n" + ">> -\t(*sps)->enc[0].pte_enc = def->penc;\n" + ">> +\t(*sps)->enc[0].pte_enc = def->penc[linux_psize];\n" ">> \t(*sps)++;\n" ">> }\n" ">\n" - "> This will only return the entries where actual page size =3D=3D base page\n" + "> This will only return the entries where actual page size == base page\n" "> size, which basically means that KVM guests won't be able to use\n" "> MPSS. We will need to return multiple entries in that case.\n" "\n" @@ -67,20 +66,20 @@ ">> +\tunsigned int mask;\n" ">> +\tint i, penc, shift;\n" ">> +\t/* Look at the 8 bit LP value */\n" - ">> +\tunsigned int lp =3D (hptep->r >> LP_SHIFT) & ((1 << LP_BITS) - 1);\n" + ">> +\tunsigned int lp = (hptep->r >> LP_SHIFT) & ((1 << LP_BITS) - 1);\n" ">> +\n" - ">> +\tpenc =3D 0;\n" - ">> +\tfor (i =3D 0; i < MMU_PAGE_COUNT; i++) {\n" + ">> +\tpenc = 0;\n" + ">> +\tfor (i = 0; i < MMU_PAGE_COUNT; i++) {\n" ">> +\t\t/* valid entries have a shift value */\n" ">> +\t\tif (!mmu_psize_defs[i].shift)\n" ">> +\t\t\tcontinue;\n" ">> +\n" ">> +\t\t/* encoding bits per actual page size */\n" - ">> +\t\tshift =3D mmu_psize_defs[i].shift - 11;\n" + ">> +\t\tshift = mmu_psize_defs[i].shift - 11;\n" ">> +\t\tif (shift > 9)\n" - ">> +\t\t\tshift =3D 9;\n" - ">> +\t\tmask =3D (1 << shift) - 1;\n" - ">> +\t\tif ((lp & mask) =3D=3D mmu_psize_defs[psize].penc[i])\n" + ">> +\t\t\tshift = 9;\n" + ">> +\t\tmask = (1 << shift) - 1;\n" + ">> +\t\tif ((lp & mask) == mmu_psize_defs[psize].penc[i])\n" ">> +\t\t\treturn i;\n" ">> +\t}\n" ">> +\treturn -1;\n" @@ -92,9 +91,9 @@ "> not the base page size.\n" "\n" "That 11 should be 12.That depends on the fact that we have below mapping\n" - " rrrr rrrz \t=E2=89=A58KB\n" + " rrrr rrrz \t\342\211\2458KB\n" "\n" - "Yes, that 9 should be LP_BITs.=20\n" + "Yes, that 9 should be LP_BITs. \n" "\n" "We are generating mask based on actual page size above (variable i in\n" "the for loop).\n" @@ -115,24 +114,23 @@ ">> +\t\t\tint *psize, int *apsize, int *ssize, unsigned long *vpn)\n" ">> {\n" ">> \tunsigned long avpn, pteg, vpi;\n" - ">> \tunsigned long hpte_r =3D hpte->r;\n" - ">> \tunsigned long hpte_v =3D hpte->v;\n" + ">> \tunsigned long hpte_r = hpte->r;\n" + ">> \tunsigned long hpte_v = hpte->v;\n" ">> \tunsigned long vsid, seg_off;\n" ">> -\tint i, size, shift, penc;\n" - ">> +\tint i, size, a_size =3D MMU_PAGE_4K, shift, penc;\n" - ">>=20=20\n" + ">> +\tint i, size, a_size = MMU_PAGE_4K, shift, penc;\n" + ">> \n" ">> \tif (!(hpte_v & HPTE_V_LARGE))\n" - ">> \t\tsize =3D MMU_PAGE_4K;\n" - ">> @@ -395,12 +422,13 @@ static void hpte_decode(struct hash_pte *hpte, uns=\n" - "igned long slot,\n" + ">> \t\tsize = MMU_PAGE_4K;\n" + ">> @@ -395,12 +422,13 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,\n" ">> \t\t\t/* valid entries have a shift value */\n" ">> \t\t\tif (!mmu_psize_defs[size].shift)\n" ">> \t\t\t\tcontinue;\n" ">> -\n" - ">> -\t\t\tif (penc =3D=3D mmu_psize_defs[size].penc)\n" + ">> -\t\t\tif (penc == mmu_psize_defs[size].penc)\n" ">> -\t\t\t\tbreak;\n" - ">> +\t\t\tfor (a_size =3D 0; a_size < MMU_PAGE_COUNT; a_size++)\n" - ">> +\t\t\t\tif (penc =3D=3D mmu_psize_defs[size].penc[a_size])\n" + ">> +\t\t\tfor (a_size = 0; a_size < MMU_PAGE_COUNT; a_size++)\n" + ">> +\t\t\t\tif (penc == mmu_psize_defs[size].penc[a_size])\n" ">> +\t\t\t\t\tgoto out;\n" ">\n" "> Once again I don't think this is correct, since the number of bits in\n" @@ -151,96 +149,95 @@ ">> static int __init htab_dt_scan_page_sizes(unsigned long node,\n" ">> \t\t\t\t\t const char *uname, int depth,\n" ">> \t\t\t\t\t void *data)\n" - ">> @@ -294,60 +318,57 @@ static int __init htab_dt_scan_page_sizes(unsigned=\n" - " long node,\n" - ">> \t\tsize /=3D 4;\n" - ">> \t\tcur_cpu_spec->mmu_features &=3D ~(MMU_FTR_16M_PAGE);\n" + ">> @@ -294,60 +318,57 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,\n" + ">> \t\tsize /= 4;\n" + ">> \t\tcur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);\n" ">> \t\twhile(size > 0) {\n" - ">> -\t\t\tunsigned int shift =3D prop[0];\n" - ">> +\t\t\tunsigned int base_shift =3D prop[0];\n" - ">> \t\t\tunsigned int slbenc =3D prop[1];\n" - ">> \t\t\tunsigned int lpnum =3D prop[2];\n" - ">> -\t\t\tunsigned int lpenc =3D 0;\n" + ">> -\t\t\tunsigned int shift = prop[0];\n" + ">> +\t\t\tunsigned int base_shift = prop[0];\n" + ">> \t\t\tunsigned int slbenc = prop[1];\n" + ">> \t\t\tunsigned int lpnum = prop[2];\n" + ">> -\t\t\tunsigned int lpenc = 0;\n" ">> \t\t\tstruct mmu_psize_def *def;\n" - ">> -\t\t\tint idx =3D -1;\n" + ">> -\t\t\tint idx = -1;\n" ">> +\t\t\tint idx, base_idx;\n" - ">>=20=20\n" - ">> \t\t\tsize -=3D 3; prop +=3D 3;\n" + ">> \n" + ">> \t\t\tsize -= 3; prop += 3;\n" ">> -\t\t\twhile(size > 0 && lpnum) {\n" - ">> -\t\t\t\tif (prop[0] =3D=3D shift)\n" - ">> -\t\t\t\t\tlpenc =3D prop[1];\n" - ">> +\t\t\tbase_idx =3D get_idx_from_shift(base_shift);\n" + ">> -\t\t\t\tif (prop[0] == shift)\n" + ">> -\t\t\t\t\tlpenc = prop[1];\n" + ">> +\t\t\tbase_idx = get_idx_from_shift(base_shift);\n" ">> +\t\t\tif (base_idx < 0) {\n" ">> +\t\t\t\t/*\n" ">> +\t\t\t\t * skip the pte encoding also\n" ">> +\t\t\t\t */\n" - ">> \t\t\t\tprop +=3D 2; size -=3D 2;\n" + ">> \t\t\t\tprop += 2; size -= 2;\n" ">> -\t\t\t\tlpnum--;\n" ">> +\t\t\t\tcontinue;\n" ">> \t\t\t}\n" ">> -\t\t\tswitch(shift) {\n" ">> -\t\t\tcase 0xc:\n" - ">> -\t\t\t\tidx =3D MMU_PAGE_4K;\n" + ">> -\t\t\t\tidx = MMU_PAGE_4K;\n" ">> -\t\t\t\tbreak;\n" ">> -\t\t\tcase 0x10:\n" - ">> -\t\t\t\tidx =3D MMU_PAGE_64K;\n" + ">> -\t\t\t\tidx = MMU_PAGE_64K;\n" ">> -\t\t\t\tbreak;\n" ">> -\t\t\tcase 0x14:\n" - ">> -\t\t\t\tidx =3D MMU_PAGE_1M;\n" + ">> -\t\t\t\tidx = MMU_PAGE_1M;\n" ">> -\t\t\t\tbreak;\n" ">> -\t\t\tcase 0x18:\n" - ">> -\t\t\t\tidx =3D MMU_PAGE_16M;\n" - ">> +\t\t\tdef =3D &mmu_psize_defs[base_idx];\n" - ">> +\t\t\tif (base_idx =3D=3D MMU_PAGE_16M)\n" - ">> \t\t\t\tcur_cpu_spec->mmu_features |=3D MMU_FTR_16M_PAGE;\n" + ">> -\t\t\t\tidx = MMU_PAGE_16M;\n" + ">> +\t\t\tdef = &mmu_psize_defs[base_idx];\n" + ">> +\t\t\tif (base_idx == MMU_PAGE_16M)\n" + ">> \t\t\t\tcur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;\n" ">> -\t\t\t\tbreak;\n" ">> -\t\t\tcase 0x22:\n" - ">> -\t\t\t\tidx =3D MMU_PAGE_16G;\n" + ">> -\t\t\t\tidx = MMU_PAGE_16G;\n" ">> -\t\t\t\tbreak;\n" ">> -\t\t\t}\n" ">> -\t\t\tif (idx < 0)\n" ">> -\t\t\t\tcontinue;\n" - ">> -\t\t\tdef =3D &mmu_psize_defs[idx];\n" - ">> -\t\t\tdef->shift =3D shift;\n" - ">> -\t\t\tif (shift <=3D 23)\n" + ">> -\t\t\tdef = &mmu_psize_defs[idx];\n" + ">> -\t\t\tdef->shift = shift;\n" + ">> -\t\t\tif (shift <= 23)\n" ">> +\n" - ">> +\t\t\tdef->shift =3D base_shift;\n" - ">> +\t\t\tif (base_shift <=3D 23)\n" - ">> \t\t\t\tdef->avpnm =3D 0;\n" + ">> +\t\t\tdef->shift = base_shift;\n" + ">> +\t\t\tif (base_shift <= 23)\n" + ">> \t\t\t\tdef->avpnm = 0;\n" ">> \t\t\telse\n" - ">> -\t\t\t\tdef->avpnm =3D (1 << (shift - 23)) - 1;\n" - ">> +\t\t\t\tdef->avpnm =3D (1 << (base_shift - 23)) - 1;\n" - ">> \t\t\tdef->sllp =3D slbenc;\n" - ">> -\t\t\tdef->penc =3D lpenc;\n" + ">> -\t\t\t\tdef->avpnm = (1 << (shift - 23)) - 1;\n" + ">> +\t\t\t\tdef->avpnm = (1 << (base_shift - 23)) - 1;\n" + ">> \t\t\tdef->sllp = slbenc;\n" + ">> -\t\t\tdef->penc = lpenc;\n" ">> -\t\t\t/* We don't know for sure what's up with tlbiel, so\n" ">> +\t\t\t/*\n" ">> +\t\t\t * We don't know for sure what's up with tlbiel, so\n" ">> \t\t\t * for now we only set it for 4K and 64K pages\n" ">> \t\t\t */\n" - ">> -\t\t\tif (idx =3D=3D MMU_PAGE_4K || idx =3D=3D MMU_PAGE_64K)\n" - ">> +\t\t\tif (base_idx =3D=3D MMU_PAGE_4K || base_idx =3D=3D MMU_PAGE_64K)\n" - ">> \t\t\t\tdef->tlbiel =3D 1;\n" + ">> -\t\t\tif (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)\n" + ">> +\t\t\tif (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)\n" + ">> \t\t\t\tdef->tlbiel = 1;\n" ">> \t\t\telse\n" - ">> \t\t\t\tdef->tlbiel =3D 0;\n" - ">>=20=20\n" - ">> -\t\t\tDBG(\" %d: shift=3D%02x, sllp=3D%04lx, avpnm=3D%08lx, \"\n" - ">> -\t\t\t \"tlbiel=3D%d, penc=3D%d\\n\",\n" + ">> \t\t\t\tdef->tlbiel = 0;\n" + ">> \n" + ">> -\t\t\tDBG(\" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, \"\n" + ">> -\t\t\t \"tlbiel=%d, penc=%d\\n\",\n" ">> -\t\t\t idx, shift, def->sllp, def->avpnm, def->tlbiel,\n" ">> -\t\t\t def->penc);\n" ">> +\t\t\twhile (size > 0 && lpnum) {\n" - ">> +\t\t\t\tunsigned int shift =3D prop[0];\n" - ">> +\t\t\t\tunsigned int penc =3D prop[1];\n" + ">> +\t\t\t\tunsigned int shift = prop[0];\n" + ">> +\t\t\t\tunsigned int penc = prop[1];\n" ">> +\n" - ">> +\t\t\t\tprop +=3D 2; size -=3D 2;\n" + ">> +\t\t\t\tprop += 2; size -= 2;\n" ">> +\t\t\t\tlpnum--;\n" ">> +\n" - ">> +\t\t\t\tidx =3D get_idx_from_shift(shift);\n" + ">> +\t\t\t\tidx = get_idx_from_shift(shift);\n" ">> +\t\t\t\tif (idx < 0)\n" ">> +\t\t\t\t\tcontinue;\n" ">> +\n" - ">> +\t\t\t\tdef->penc[idx] =3D penc;\n" - ">> +\t\t\t\tDBG(\" %d: shift=3D%02x, sllp=3D%04lx, \"\n" - ">> +\t\t\t\t \"avpnm=3D%08lx, tlbiel=3D%d, penc=3D%d\\n\",\n" + ">> +\t\t\t\tdef->penc[idx] = penc;\n" + ">> +\t\t\t\tDBG(\" %d: shift=%02x, sllp=%04lx, \"\n" + ">> +\t\t\t\t \"avpnm=%08lx, tlbiel=%d, penc=%d\\n\",\n" ">> +\t\t\t\t idx, shift, def->sllp, def->avpnm,\n" ">> +\t\t\t\t def->tlbiel, def->penc[idx]);\n" ">> +\t\t\t}\n" @@ -252,15 +249,20 @@ "\n" "--- a/arch/powerpc/mm/hash_utils_64.c\n" "+++ b/arch/powerpc/mm/hash_utils_64.c\n" - "@@ -125,7 +125,7 @@ static struct mmu_psize_def mmu_psize_defaults_old[] =\n" - "=3D {\n" - " [MMU_PAGE_4K] =3D {\n" - " .shift =3D 12,\n" - " .sllp =3D 0,\n" - "- .penc =3D 0,\n" - "+ .penc =3D { [0 ... MMU_PAGE_COUNT - 1] =3D -1 },\n" - " .avpnm =3D 0,\n" + "@@ -125,7 +125,7 @@ static struct mmu_psize_def mmu_psize_defaults_old[] = {\n" + " [MMU_PAGE_4K] = {\n" + " .shift = 12,\n" + " .sllp = 0,\n" + "- .penc = 0,\n" + "+ .penc = { [0 ... MMU_PAGE_COUNT - 1] = -1 },\n" + " .avpnm = 0,\n" "\n" - -aneesh + "-aneesh\n" + "\n" + "--\n" + "To unsubscribe, send a message with 'unsubscribe linux-mm' in\n" + "the body to majordomo@kvack.org. For more info on Linux MM,\n" + "see: http://www.linux-mm.org/ .\n" + "Don't email: <a href=mailto:\"dont@kvack.org\"> email@kvack.org </a>" -8ec2afab1af5d8de8959980b33ca96ba4b9db3ab9fe9ff17dd1141021c0f0d3e +d0beb923ef832f4f4413ccc2cc2c950deed68ce09fc29a19b230c4e7a1131ac3
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.