From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1K2iL8-0005V1-3L for qemu-devel@nongnu.org; Sun, 01 Jun 2008 03:50:54 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1K2iL7-0005Ty-84 for qemu-devel@nongnu.org; Sun, 01 Jun 2008 03:50:53 -0400 Received: from [199.232.76.173] (port=46615 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1K2iL7-0005To-3Z for qemu-devel@nongnu.org; Sun, 01 Jun 2008 03:50:53 -0400 Received: from mk-outboundfilter-3.mail.uk.tiscali.com ([212.74.114.23]:53171) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1K2iL6-00084K-C8 for qemu-devel@nongnu.org; Sun, 01 Jun 2008 03:50:52 -0400 From: Richard Sandiford References: Date: Sun, 01 Jun 2008 08:50:46 +0100 In-Reply-To: (Thiemo Seufer's message of "Fri\, 30 May 2008 00\:12\:53 +0000") Message-ID: <87y75pzj8p.fsf@firetop.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Subject: [Qemu-devel] Re: [4622] Fix for 32-bit MIPS. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hi Thiemo, Thanks for applying the patches, and sorry for the fallout on 32-bit targets from the DIV patch. Thiemo Seufer writes: > @@ -1904,15 +1904,16 @@ > { > TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64); > TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); > + TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64); > > - tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); > - tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); > - tcg_gen_div_i64(r_tmp1, cpu_T[0], cpu_T[1]); > - tcg_gen_rem_i64(r_tmp2, cpu_T[0], cpu_T[1]); > - tcg_gen_ext32s_tl(r_tmp1, r_tmp1); > - tcg_gen_ext32s_tl(r_tmp2, r_tmp2); > - gen_store_LO(r_tmp1, 0); > - gen_store_HI(r_tmp2, 0); > + tcg_gen_ext_tl_i64(r_tmp1, cpu_T[0]); > + tcg_gen_ext_tl_i64(r_tmp2, cpu_T[1]); > + tcg_gen_div_i64(r_tmp3, r_tmp1, r_tmp2); > + tcg_gen_rem_i64(r_tmp2, r_tmp1, r_tmp2); > + tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp3); > + tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp2); > + gen_store_LO(cpu_T[0], 0); > + gen_store_HI(cpu_T[1], 0); > } > gen_set_label(l1); > } This isn't quite right for 64-bit targets. Both pairs of "ext32s"s really were needed. The input pair were needed so that we don't trigger the SIGFPE for unpredictable cases in which the source operands are not sign-extended. (Should never happen, of course, but it's a pain if it crashes the emulator.) The output pair are needed so that the 32-bit result is correctly sign-extended. E.g., with the problem case of 0xffffffff80000000 / -1, the result is now 0x0000000080000000 instead of 0xffffffff80000000. In other words, I think we need both the ext32s_tl and the ext_tl_i64/ trunc_i64_tl operations. Sorry for not picking this up in the original submission. Richard