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Tue, 07 Apr 2026 03:35:21 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9c3d028831sm535165566b.59.2026.04.07.03.35.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Apr 2026 03:35:21 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 778745F9CD; Tue, 07 Apr 2026 11:35:20 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org Subject: Re: [RFC PATCH 27/35] target/arm: wrap event_register in a union In-Reply-To: <0877e0da-c083-4293-bba2-5c1d2e2315b7@linaro.org> (Richard Henderson's message of "Mon, 6 Apr 2026 10:37:17 +1000") References: <20260320130607.2071996-1-alex.bennee@linaro.org> <20260320130607.2071996-28-alex.bennee@linaro.org> <0877e0da-c083-4293-bba2-5c1d2e2315b7@linaro.org> User-Agent: mu4e 1.14.1-pre1; emacs 30.1 Date: Tue, 07 Apr 2026 11:35:20 +0100 Message-ID: <87zf3fawif.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Richard Henderson writes: > On 3/21/26 00:05, Alex Benn=C3=A9e wrote: >> While the event register is either set or not due to the >> implementation defined nature of bool types we can't set it directly >> from TCG code. By wrapping in a union we can alias a 32 bit value to >> the bool in a future patch. >> Signed-off-by: Alex Benn=C3=A9e >> --- >> target/arm/cpu.h | 9 +++++++-- >> hw/intc/armv7m_nvic.c | 2 +- >> target/arm/machine.c | 4 ++-- >> target/arm/tcg/m_helper.c | 4 ++-- >> target/arm/tcg/op_helper.c | 6 +++--- >> 5 files changed, 15 insertions(+), 10 deletions(-) >> diff --git a/target/arm/cpu.h b/target/arm/cpu.h >> index bf6cf74c2e1..9c25b60ae83 100644 >> --- a/target/arm/cpu.h >> +++ b/target/arm/cpu.h >> @@ -763,9 +763,14 @@ typedef struct CPUArchState { >> /* >> * The event register is shared by all ARM profiles (A/R/M), >> * so it is stored in the top-level CPU state. >> - * WFE/SEV handling is currently implemented only for M-profile. >> + * >> + * It is treated as a boolean but we need the union so we can set >> + * it from TCG. >> */ >> - bool event_register; >> + union { >> + bool as_bool; >> + uint32_t as_uint32; >> + } event_register; > > What are you attempting here? This smells like a big-endian bug. > > TCG is certainly capable of storing to a bool, via tcg_gen_st8_*. So the problem I had was I don't know what size bool will be as its up to each architecture to define the size. I originally had a compile time assert but that failed. Hence this hack to put something that would plausibly overlap. I wonder if there would be a way to use a Generic so tcg_gen_st8_bool would always map to the right size whichever arch we are on? > > > r~ --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro