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Tue, 26 Aug 2025 20:16:39 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 94412928-82b9-11f0-b898-0df219b8e170 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CtgOOiCc8cPCMWvGEcslAuVznnII2zRf/c3O05int/4BNre0wlN9K9a8Pf0qxNVSiOzTTZfGlJFpWlDvKDrhMnuglqtq9fXe2GqX6QlCv3kjBSTEhdy/d/jHkbu5HNoWcKsCiDjFW53H6aFm0AeVyjN3ooxBdnBhOTXcIAvJEiD3aW2Z8ngIccB/a7+MDwx3qy2n4/7HR0tZnaiHcwa3DjDcM7DkuzxQHxdTVLZsDkUaToZL7983vvp+T1a7ohjJJaUwgthDTHY9JASGWIfaKWzMUguxSgiD5P3v1RLy1Smj68Vec7dmjzpsEP51cFpeR96swIHr7WWL/LVrdYAH8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4ETeGl12XGv6FyPiROn1jEG1DqEW8h5hgkx+DXtLTZ0=; b=P/eMWOEbVTVLE40JOKooQ9rojH7GWcM6R+XOpYVLlkxHgJN3GBV0LN3ur3l7AzTQRn0j4G9OG40xrYC9Uemc8t3XDBLev99H0Yr6t21pYaQyB1z5lzYksF+pQgL+AAEU3BCGi6AFB8TIr+hxuuJSjkFB0HjC7armtvaSP4ckV3rjkOv/NjaKkxWYVSih72tahcWFusmN8F988NRbo+PsWso+Eq6moXE7Ct7uBU4Hc5IuzISMa2FdBLrUg9Eb3us3hVtOKcfczQCSiaBWhmKZ+f992L1a5GZg1KqT3v79yjNUc81h0gKZl9/jDnr7mxTA9+8tXgi8FLZHWninmCxuQg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=epam.com; dmarc=pass action=none header.from=epam.com; dkim=pass header.d=epam.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=epam.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4ETeGl12XGv6FyPiROn1jEG1DqEW8h5hgkx+DXtLTZ0=; b=ZnKQ4Xw7NjwNYZ0L5vMA+2PeADbRcLZi6TEZTBX0h/gR0FW3GmeXPJ9Tjr8J7DnZMLyj6lbMUhyhZMHbkG61LVkDDnG43MXE/b2gdmbEheBsYd1/Z2JNhmjiV/XK9xq8MW/815fYftfCGrqFJUOqcU1lKSa+v57emzBYiAm8D5Uf7wdRyXaWOUKOMYgIJPLDOILaRw/QLKbr3Y8bCO5lTrFf2N+C7lGXo2zqkVjKdFj7c3hU3I4gj9dGwHFZegYNhCxD5v8jHWosflIliHnr/6mM8f0C9PdqWV+QV2IiwIapRyxHHHigUX/qZKsxuhy1qg1VHMeLNy4oEGd0JKwslA== From: Volodymyr Babchuk To: Leonid Komarianskyi CC: "xen-devel@lists.xenproject.org" , "olekstysh@gmail.com" , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel Subject: Re: [PATCH v3 04/11] xen/arm/irq: add handling for IRQs in the eSPI range Thread-Topic: [PATCH v3 04/11] xen/arm/irq: add handling for IRQs in the eSPI range Thread-Index: AQHcFpJ/t39ssss6a0y8SPAQeD5PEA== Date: Tue, 26 Aug 2025 20:16:39 +0000 Message-ID: <87zfbl4z4p.fsf@epam.com> References: <8b42416d779537d6a0ac4902cabc549253b9da9d.1756216943.git.leonid_komarianskyi@epam.com> In-Reply-To: <8b42416d779537d6a0ac4902cabc549253b9da9d.1756216943.git.leonid_komarianskyi@epam.com> (Leonid Komarianskyi's message of "Tue, 26 Aug 2025 14:05:37 +0000") Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV1PR03MB10456.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3a62177e-bb95-477b-af35-08dde4dd7741 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Aug 2025 20:16:39.6080 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 9pa3SGRQE/L5hTDU2wbHWd1PUjyn2bwv32YFLcw1o1hXSfyY1KBBhP8AH0ImVQaNRpLyDADu9op/QFlwlkidLcZgd5Iwf1Hep8UhwedXSR4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB7521 Hi Leonid, Leonid Komarianskyi writes: > Currently, Xen does not support eSPI interrupts, leading > to a data abort when such interrupts are defined in the DTS. > > This patch introduces a separate array to initialize up to > 1024 interrupt descriptors in the eSPI range and adds the > necessary defines and helper function. These changes lay the > groundwork for future implementation of full eSPI interrupt > support. As this GICv3.1 feature is not required by all vendors, > all changes are guarded by ifdefs, depending on the corresponding > Kconfig option. > > Signed-off-by: Leonid Komarianskyi Reviewed-by: Volodymyr Babchuk > > --- > Changes in V2: > - use (ESPI_MAX_INTID + 1) instead of (ESPI_BASE_INTID + NR_IRQS) > - remove unnecessary comment for nr_irqs initialization > > Changes in V3: > - introduced a new define NR_ESPI_IRQS to avoid confusion, like in the > case of using NR_IRQS for espi_desc array > - implemented helper functions espi_to_desc and init_espi_data to make > it possible to add stubs with the same name, and as a result, reduce > the number of #ifdefs > - change CONFIG_GICV3_ESPI default value to n > --- > xen/arch/arm/Kconfig | 9 ++++++ > xen/arch/arm/include/asm/irq.h | 26 +++++++++++++++++ > xen/arch/arm/irq.c | 52 +++++++++++++++++++++++++++++++++- > 3 files changed, 86 insertions(+), 1 deletion(-) > > diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig > index 17df147b25..5813e5b267 100644 > --- a/xen/arch/arm/Kconfig > +++ b/xen/arch/arm/Kconfig > @@ -135,6 +135,15 @@ config GICV3 > Driver for the ARM Generic Interrupt Controller v3. > If unsure, use the default setting. > =20 > +config GICV3_ESPI > + bool "Extended SPI range support" > + depends on GICV3 && !NEW_VGIC > + default n > + help > + Allow Xen and domains to use interrupt numbers from the extended SPI > + range, from 4096 to 5119. This feature is introduced in GICv3.1 > + architecture. > + > config HAS_ITS > bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPO= RTED > depends on GICV3 && !NEW_VGIC && !ARM_32 > diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/ir= q.h > index 5bc6475eb4..221dbf23a2 100644 > --- a/xen/arch/arm/include/asm/irq.h > +++ b/xen/arch/arm/include/asm/irq.h > @@ -32,6 +32,15 @@ struct arch_irq_desc { > #define SPI_MAX_INTID 1019 > #define LPI_OFFSET 8192 > =20 > +#ifdef CONFIG_GICV3_ESPI > +#define ESPI_BASE_INTID 4096 > +#define ESPI_MAX_INTID 5119 > +#define NR_ESPI_IRQS 1024 > + > +#define ESPI_INTID2IDX(intid) ((intid) - ESPI_BASE_INTID) > +#define ESPI_IDX2INTID(idx) ((idx) + ESPI_BASE_INTID) > +#endif > + > /* LPIs are always numbered starting at 8192, so 0 is a good invalid cas= e. */ > #define INVALID_LPI 0 > =20 > @@ -39,7 +48,15 @@ struct arch_irq_desc { > #define INVALID_IRQ 1023 > =20 > extern const unsigned int nr_irqs; > +#ifdef CONFIG_GICV3_ESPI > +/* > + * This will also cover the eSPI range, as some critical devices > + * for booting Xen (e.g., serial) may use this type of interrupts. > + */ > +#define nr_static_irqs (ESPI_MAX_INTID + 1) > +#else > #define nr_static_irqs NR_IRQS > +#endif > =20 > struct irq_desc; > struct irqaction; > @@ -55,6 +72,15 @@ static inline bool is_lpi(unsigned int irq) > return irq >=3D LPI_OFFSET; > } > =20 > +static inline bool is_espi(unsigned int irq) > +{ > +#ifdef CONFIG_GICV3_ESPI > + return (irq >=3D ESPI_BASE_INTID && irq <=3D ESPI_MAX_INTID); > +#else > + return false; > +#endif > +} > + > #define domain_pirq_to_irq(d, pirq) (pirq) > =20 > bool is_assignable_irq(unsigned int irq); > diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c > index b8eccfc924..adb5e49ea3 100644 > --- a/xen/arch/arm/irq.c > +++ b/xen/arch/arm/irq.c > @@ -19,7 +19,11 @@ > #include > #include > =20 > +#ifdef CONFIG_GICV3_ESPI > +const unsigned int nr_irqs =3D ESPI_MAX_INTID + 1; > +#else > const unsigned int nr_irqs =3D NR_IRQS; > +#endif > =20 > static unsigned int local_irqs_type[NR_LOCAL_IRQS]; > static DEFINE_SPINLOCK(local_irqs_type_lock); > @@ -46,6 +50,49 @@ void irq_end_none(struct irq_desc *irq) > } > =20 > static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS]; > +#ifdef CONFIG_GICV3_ESPI > +static irq_desc_t espi_desc[NR_ESPI_IRQS]; > + > +static struct irq_desc *espi_to_desc(unsigned int irq) > +{ > + return &espi_desc[ESPI_INTID2IDX(irq)]; > +} > + > +static int __init init_espi_data(void) > +{ > + int irq; > + > + for ( irq =3D ESPI_BASE_INTID; irq <=3D ESPI_MAX_INTID; irq++ ) > + { > + struct irq_desc *desc =3D irq_to_desc(irq); > + int rc =3D init_one_irq_desc(desc); > + > + if ( rc ) > + return rc; > + > + desc->irq =3D irq; > + desc->action =3D NULL; > + } > + > + return 0; > +} > +#else > +/* > + * This function is stub and will not be called if CONFIG_GICV3_ESPI=3Dn= , > + * because in this case, is_espi will always return false. > + */ > +static struct irq_desc *espi_to_desc(unsigned int irq) > +{ > + ASSERT_UNREACHABLE(); > + return NULL; > +} > + > +static int __init init_espi_data(void) > +{ > + return 0; > +} > +#endif > + > static DEFINE_PER_CPU(irq_desc_t[NR_LOCAL_IRQS], local_irq_desc); > =20 > struct irq_desc *__irq_to_desc(unsigned int irq) > @@ -53,6 +100,9 @@ struct irq_desc *__irq_to_desc(unsigned int irq) > if ( irq < NR_LOCAL_IRQS ) > return &this_cpu(local_irq_desc)[irq]; > =20 > + if ( is_espi(irq) ) > + return espi_to_desc(irq); > + > return &irq_desc[irq-NR_LOCAL_IRQS]; > } > =20 > @@ -79,7 +129,7 @@ static int __init init_irq_data(void) > desc->action =3D NULL; > } > =20 > - return 0; > + return init_espi_data(); > } > =20 > static int init_local_irq_data(unsigned int cpu) --=20 WBR, Volodymyr=