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Sat, 23 Aug 2025 00:20:55 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0a429c1b-7fb7-11f0-b898-0df219b8e170 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DBdnGm5V8PnitTekWgtZ2WNDm37NMiV+ba1lKZg8h8/ZfuyrzfB7UvEaa6oqH0M/t6XJUn+nHXwUvDkmKSAXS3bios1zSCGlptFFjnxNtx8ctGjj5m6o4zv84yPS+8lrisc9eYCGAoBgvevgCNDtcS4dtFwDZFwAPkpMrAb5qjvxtstC719Ibi2WXJobJ1AoykDxy/WQHWkJBQpoLUroCwGMT7hmA4SsnpnOMrhc+7RVfN2LkMA0hHHgcNqX5ZJ4cXeInjluF3ho5jB+M9TWd9yVjQ77m179pwwOOzsORQCPTp5qZob6wdpKXPo4FHWW56qIgWzqKYpbH0o4G40Pug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV1PR03MB10456.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 73c28470-ff9d-478e-3ccf-08dde1daed2c X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Aug 2025 00:20:55.4519 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fjLsuaQ1JGK6tZgGSY56krdTT6s8gFQmFjNqpHzBg+apolq4aRAknk2tLFHbkOesKON226Nffe+caOV9/CTyMXLfUCFn7tKJJ0wqsNsSKws= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR03MB10195 Hi, Mykola Kvach writes: > From: Mykola Kvach > > System suspend may lead to a state where GIC would be powered down. > Therefore, Xen should save/restore the context of GIC on suspend/resume. > > Note that the context consists of states of registers which are > controlled by the hypervisor. Other GIC registers which are accessible > by guests are saved/restored on context switch. > > Signed-off-by: Mykola Kvach > --- > xen/arch/arm/gic-v3.c | 233 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 233 insertions(+) > > diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c > index cd3e1acf79..a9b65ff5d4 100644 > --- a/xen/arch/arm/gic-v3.c > +++ b/xen/arch/arm/gic-v3.c > @@ -1776,6 +1776,231 @@ static bool gic_dist_supports_lpis(void) > return (readl_relaxed(GICD + GICD_TYPER) & GICD_TYPE_LPIS); > } > =20 > +#ifdef CONFIG_SYSTEM_SUSPEND > + > +/* GICv3 registers to be saved/restored on system suspend/resume */ > +struct gicv3_ctx { > + struct dist_ctx { > + uint32_t ctlr; > + /* > + * This struct represent block of 32 IRQs > + * TODO: store extended SPI configuration (GICv3.1+) > + */ > + struct irq_regs { > + uint32_t icfgr[2]; > + uint32_t ipriorityr[8]; > + uint64_t irouter[32]; > + uint32_t isactiver; > + uint32_t isenabler; > + } *irqs; > + } dist; > + > + /* have only one rdist structure for last running CPU during suspend= */ > + struct redist_ctx { > + uint32_t ctlr; > + /* TODO: handle case when we have more than 16 PPIs (GICv3.1+) *= / > + uint32_t icfgr[2]; > + uint32_t igroupr; > + uint32_t ipriorityr[8]; > + uint32_t isactiver; > + uint32_t isenabler; > + } rdist; > + > + struct cpu_ctx { > + uint32_t ctlr; > + uint32_t pmr; > + uint32_t bpr; > + uint32_t sre_el2; > + uint32_t grpen; > + } cpu; > +}; > + > +static struct gicv3_ctx gicv3_ctx; > + > +static void __init gicv3_alloc_context(void) > +{ > + uint32_t blocks =3D DIV_ROUND_UP(gicv3_info.nr_lines, 32); > + > + if ( gicv3_its_host_has_its() ) > + return; I think this needs a comment at least. And/or printk() message. Because for it is unclear why we are doing nothing if host has ITS > + > + /* according to spec it is possible don't have SPIs */ > + if ( blocks =3D=3D 1 ) > + return; > + > + gicv3_ctx.dist.irqs =3D xzalloc_array(typeof(*gicv3_ctx.dist.irqs), = blocks - 1); > + if ( !gicv3_ctx.dist.irqs ) > + dprintk(XENLOG_ERR, > + "%s:%d: failed to allocate memory for GICv3 suspend cont= ext\n", > + __func__, __LINE__); dprintk() already prints function and line. Here and everywhere in this patch. > +} > + > +static void gicv3_disable_redist(void) > +{ > + void __iomem* waker =3D GICD_RDIST_BASE + GICR_WAKER; > + > + writel_relaxed(readl_relaxed(waker) | GICR_WAKER_ProcessorSleep, wak= er); > + while ( (readl_relaxed(waker) & GICR_WAKER_ChildrenAsleep) =3D=3D 0 = ); > +} > + > +static int gicv3_suspend(void) > +{ > + unsigned int i; > + void __iomem *base; > + typeof(gicv3_ctx.rdist)* rdist =3D &gicv3_ctx.rdist; > + > + /* TODO: implement support for ITS */ > + if ( gicv3_its_host_has_its() ) > + return -EOPNOTSUPP; > + > + if ( !gicv3_ctx.dist.irqs && gicv3_info.nr_lines > NR_GIC_LOCAL_IRQS= ) > + { > + dprintk(XENLOG_WARNING, > + "%s:%d: GICv3 suspend context is not allocated!\n", > + __func__, __LINE__); > + return -ENOMEM; > + } > + > + gicv3_save_state(current); > + > + /* Save GICC configuration */ > + gicv3_ctx.cpu.ctlr =3D READ_SYSREG(ICC_CTLR_EL1); > + gicv3_ctx.cpu.pmr =3D READ_SYSREG(ICC_PMR_EL1); > + gicv3_ctx.cpu.bpr =3D READ_SYSREG(ICC_BPR1_EL1); > + gicv3_ctx.cpu.sre_el2 =3D READ_SYSREG(ICC_SRE_EL2); > + gicv3_ctx.cpu.grpen =3D READ_SYSREG(ICC_IGRPEN1_EL1); > + > + gicv3_disable_interface(); > + gicv3_disable_redist(); > + > + /* Save GICR configuration */ > + gicv3_redist_wait_for_rwp(); > + > + base =3D GICD_RDIST_SGI_BASE; > + > + rdist->ctlr =3D readl_relaxed(base + GICR_CTLR); > + > + /* Set priority on PPI and SGI interrupts */ Probably you wanted to say "Save priority..." > + for (i =3D 0; i < NR_GIC_LOCAL_IRQS / 4; i +=3D 4) > + rdist->ipriorityr[i] =3D readl_relaxed(base + GICR_IPRIORITYR0 += 4 * i); Is this correct? You are writing to every 4th rdist->ipriorityr and reading every 4th GICR_IPRIORITYR > + > + rdist->isactiver =3D readl_relaxed(base + GICR_ISACTIVER0); > + rdist->isenabler =3D readl_relaxed(base + GICR_ISENABLER0); > + rdist->igroupr =3D readl_relaxed(base + GICR_IGROUPR0); > + rdist->icfgr[0] =3D readl_relaxed(base + GICR_ICFGR0); > + rdist->icfgr[1] =3D readl_relaxed(base + GICR_ICFGR1); > + > + /* Save GICD configuration */ > + gicv3_dist_wait_for_rwp(); > + gicv3_ctx.dist.ctlr =3D readl_relaxed(GICD + GICD_CTLR); > + > + for ( i =3D 1; i < DIV_ROUND_UP(gicv3_info.nr_lines, 32); i++ ) > + { > + typeof(gicv3_ctx.dist.irqs) irqs =3D gicv3_ctx.dist.irqs + i - 1= ; > + unsigned int irq; > + > + base =3D GICD + GICD_ICFGR + 8 * i; > + irqs->icfgr[0] =3D readl_relaxed(base); > + irqs->icfgr[1] =3D readl_relaxed(base + 4); > + > + base =3D GICD + GICD_IPRIORITYR + 32 * i; > + for ( irq =3D 0; irq < 8; irq++ ) > + irqs->ipriorityr[irq] =3D readl_relaxed(base + 4 * irq); > + > + base =3D GICD + GICD_IROUTER + 32 * i; > + for ( irq =3D 0; irq < 32; irq++ ) > + irqs->irouter[irq] =3D readq_relaxed_non_atomic(base + 8 * i= rq); > + > + irqs->isactiver =3D readl_relaxed(GICD + GICD_ISACTIVER + 4 * i)= ; > + irqs->isenabler =3D readl_relaxed(GICD + GICD_ISENABLER + 4 * i)= ; > + } > + > + return 0; > +} > + > +static void gicv3_resume(void) > +{ > + unsigned int i; > + void __iomem *base; > + typeof(gicv3_ctx.rdist)* rdist =3D &gicv3_ctx.rdist; > + > + if ( !gicv3_ctx.dist.irqs && gicv3_info.nr_lines > NR_GIC_LOCAL_IRQS= ) > + { > + dprintk(XENLOG_WARNING, "%s:%d: GICv3 suspend context not alloca= ted!\n", > + __func__, __LINE__); > + return; > + } > + > + writel_relaxed(0, GICD + GICD_CTLR); > + > + for ( i =3D NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i +=3D 32 ) > + writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * = 4); > + > + for ( i =3D 1; i < DIV_ROUND_UP(gicv3_info.nr_lines, 32); i++ ) > + { > + typeof(gicv3_ctx.dist.irqs) irqs =3D gicv3_ctx.dist.irqs + i - 1= ; > + unsigned int irq; > + > + base =3D GICD + GICD_ICFGR + 8 * i; > + writel_relaxed(irqs->icfgr[0], base); > + writel_relaxed(irqs->icfgr[1], base + 4); > + > + base =3D GICD + GICD_IPRIORITYR + 32 * i; > + for ( irq =3D 0; irq < 8; irq++ ) > + writel_relaxed(irqs->ipriorityr[irq], base + 4 * irq ); style: space before ) > + > + base =3D GICD + GICD_IROUTER + 32 * i; > + for ( irq =3D 0; irq < 32; irq++ ) > + writeq_relaxed_non_atomic(irqs->irouter[irq], base + 8 * irq= ); > + > + writel_relaxed(irqs->isenabler, GICD + GICD_ISENABLER + i * 4); > + writel_relaxed(irqs->isactiver, GICD + GICD_ISACTIVER + i * 4); > + } > + > + writel_relaxed(gicv3_ctx.dist.ctlr, GICD + GICD_CTLR); > + gicv3_dist_wait_for_rwp(); > + > + /* Restore GICR (Redistributor) configuration */ > + gicv3_enable_redist(); > + > + base =3D GICD_RDIST_SGI_BASE; > + > + writel_relaxed(0xffffffff, base + GICR_ICENABLER0); > + gicv3_redist_wait_for_rwp(); > + > + for (i =3D 0; i < NR_GIC_LOCAL_IRQS / 4; i +=3D 4) > + writel_relaxed(rdist->ipriorityr[i], base + GICR_IPRIORITYR0 + i= * 4); Is this correct? You are writing to every 4th GICR_IPRIORITYR > + > + writel_relaxed(rdist->isactiver, base + GICR_ISACTIVER0); > + > + writel_relaxed(rdist->igroupr, base + GICR_IGROUPR0); > + writel_relaxed(rdist->icfgr[0], base + GICR_ICFGR0); > + writel_relaxed(rdist->icfgr[1], base + GICR_ICFGR1); > + > + gicv3_redist_wait_for_rwp(); > + > + writel_relaxed(rdist->isenabler, base + GICR_ISENABLER0); > + writel_relaxed(rdist->ctlr, GICD_RDIST_BASE + GICR_CTLR); > + > + gicv3_redist_wait_for_rwp(); > + > + WRITE_SYSREG(gicv3_ctx.cpu.sre_el2, ICC_SRE_EL2); > + isb(); > + > + /* Restore CPU interface (System registers) */ > + WRITE_SYSREG(gicv3_ctx.cpu.pmr, ICC_PMR_EL1); > + WRITE_SYSREG(gicv3_ctx.cpu.bpr, ICC_BPR1_EL1); > + WRITE_SYSREG(gicv3_ctx.cpu.ctlr, ICC_CTLR_EL1); > + WRITE_SYSREG(gicv3_ctx.cpu.grpen, ICC_IGRPEN1_EL1); > + isb(); > + > + gicv3_hyp_init(); > + > + gicv3_restore_state(current); > +} > + > +#endif /* CONFIG_SYSTEM_SUSPEND */ > + > /* Set up the GIC */ > static int __init gicv3_init(void) > { > @@ -1850,6 +2075,10 @@ static int __init gicv3_init(void) > =20 > gicv3_hyp_init(); > =20 > +#ifdef CONFIG_SYSTEM_SUSPEND > + gicv3_alloc_context(); > +#endif > + > out: > spin_unlock(&gicv3.lock); > =20 > @@ -1889,6 +2118,10 @@ static const struct gic_hw_operations gicv3_ops = =3D { > #endif > .iomem_deny_access =3D gicv3_iomem_deny_access, > .do_LPI =3D gicv3_do_LPI, > +#ifdef CONFIG_SYSTEM_SUSPEND > + .suspend =3D gicv3_suspend, > + .resume =3D gicv3_resume, > +#endif > }; > =20 > static int __init gicv3_dt_preinit(struct dt_device_node *node, const vo= id *data) --=20 WBR, Volodymyr=