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arc=none smtp.client-ip=217.70.183.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="LUT8tmpl" Received: by mail.gandi.net (Postfix) with ESMTPSA id E38A760003; Fri, 13 Dec 2024 11:20:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1734088827; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dgs5eEtaoC2aOQnCdg0dxxuEk8iGEvez1t1Gap2xNtg=; b=LUT8tmplMj5AlS5Pmj6PujybGRR/KCUjZQg6wtQ5+toJ1LogUfipwMkBK8DGjM1fYSTa3r 7xdoV0aD+HCtZ+6lsfgJSRj1Ka7QqBYeqW0L+5SBCdkzXaLVrgXiyBs7J0yH6L9QwfR7lR q3553a1OhAiRNpE21nuxcnKHPHo46+qjM9tfPrISHEtiKD/h7fy46oGGbpMYWShp4Gx9EA uRXkCcTHeIy9jAweI3hmSkcQa0lLjGzkREFWqxnedt+g/3DKpXhSJM061REWHPltQDIIGC IU/AMbQQ00uqXV5rydqO9HMrRRJAXzBQ5pc4SQae+dJCmghi1JnV2Te24bWclw== From: Miquel Raynal To: Tudor Ambarus Cc: Richard Weinberger , Vignesh Raghavendra , Pratyush Yadav , Michael Walle , linux-mtd@lists.infradead.org, Mark Brown , linux-spi@vger.kernel.org, Steam Lin , Thomas Petazzoni , Sanjay R Mehta , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek Subject: Re: [PATCH 03/24] spi: amd: Support per spi-mem operation frequency switches In-Reply-To: <64ade17d-3800-4afc-847c-b8e5fc5d7360@linaro.org> (Tudor Ambarus's message of "Mon, 11 Nov 2024 13:36:15 +0000") References: <20241025161501.485684-1-miquel.raynal@bootlin.com> <20241025161501.485684-4-miquel.raynal@bootlin.com> <64ade17d-3800-4afc-847c-b8e5fc5d7360@linaro.org> User-Agent: mu4e 1.12.7; emacs 29.4 Date: Fri, 13 Dec 2024 12:20:25 +0100 Message-ID: <87zfkzn81y.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: miquel.raynal@bootlin.com Hi Tudor, On 11/11/2024 at 13:36:15 GMT, Tudor Ambarus wro= te: > On 10/25/24 5:14 PM, Miquel Raynal wrote: >> Every ->exec_op() call correctly configures the spi bus speed to the >> maximum allowed frequency for the memory using the constant spi default >> parameter. Since we can now have per-operation constraints, let's use >> the value that comes from the spi-mem operation structure instead. In >> case there is no specific limitation for this operation, the default spi >> device value will be given anyway. >>=20 >> This controller however performed a frequency check, which is also >> observed during the ->check_op() phase. >>=20 >> The per-operation frequency capability is thus advertised to the spi-mem >> core. >>=20 >> Cc: Sanjay R Mehta >> Signed-off-by: Miquel Raynal >> --- >> drivers/spi/spi-amd.c | 10 +++++++++- >> 1 file changed, 9 insertions(+), 1 deletion(-) >>=20 >> diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c >> index 2245ad54b03a..f58dc6375582 100644 >> --- a/drivers/spi/spi-amd.c >> +++ b/drivers/spi/spi-amd.c >> @@ -368,6 +368,9 @@ static bool amd_spi_supports_op(struct spi_mem *mem, >> op->data.buswidth > 1 || op->data.nbytes > AMD_SPI_MAX_DATA) >> return false; >>=20=20 >> + if (op->max_freq < AMD_SPI_MIN_HZ) > > How about using mem->spi->controller->min_speed_hz intead? Good idea. I think I used AMD_SPI_MIN_HZ to follow what was done somewhere else, but that's fine. > >> + return false; > > I find the check fine here, but I see however that amd_set_spi_freq() > duplicates the same, returning -EINVAL when speed_hz < AMD_SPI_MIN_HZ This one is useless, the spi core already takes care of this check, I'll drop it in a separate patch. >> + >> return spi_mem_default_supports_op(mem, op); >> } >>=20=20 >> @@ -443,7 +446,7 @@ static int amd_spi_exec_mem_op(struct spi_mem *mem, >>=20=20 >> amd_spi =3D spi_controller_get_devdata(mem->spi->controller); >>=20=20 >> - ret =3D amd_set_spi_freq(amd_spi, mem->spi->max_speed_hz); >> + ret =3D amd_set_spi_freq(amd_spi, op->max_freq); >> if (ret) >> return ret; > > however the return code is checked just on this call, and completely > ignored in the 2 other calls. I find the code a bit ugly for the non > SPIMEM case, but maybe something for the amd owner to address. Once the above check removed (it does not make much sense there), the function can return void. Cheers, Miqu=C3=A8l