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AJvYcCUwDxC1YPaLism4Ue9tX2mxhggTjmM4ljsNlJFrG/ZvqFdtmBOWPJuQBrpY35RQo/q7Sg2Phdn2@lists.linux.dev X-Gm-Message-State: AOJu0YyqDrsJtxFAfOLjhqM3lPbyFw/3sZ2Vfptr3Bp0aRFlOBxl95bK ep5N9T9YPT7PaVzUI3l97W/e2RwyB6SPkSIN7jRjxA3vM32TsdKJ X-Google-Smtp-Source: AGHT+IHktpwXMgBevNF1E9lJRm1FoQNPotb9WWsAGyYNvfz30C+K34qu3Qb8DN+2e1Pe9dVQvTz87w== X-Received: by 2002:a05:600c:4fd4:b0:426:6326:4cec with SMTP id 5b1f17b1804b1-4311df8d5e9mr10415455e9.29.1728632466401; Fri, 11 Oct 2024 00:41:06 -0700 (PDT) Received: from pyro ([2a01:e0a:19b:3cd0:989a:5c4b:b7ff:baf]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-430ccf51834sm67807515e9.26.2024.10.11.00.41.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2024 00:41:05 -0700 (PDT) From: Philippe Gerum To: Florian Bezdeka Cc: Jan Kiszka , shannmu , xenomai@lists.linux.dev, "Schaffner, Tobias (T CED SES-DE)" Subject: Re: [PATCH 1/3] RISC-V: enable IRQ-PIPELINE In-Reply-To: (Florian Bezdeka's message of "Fri, 11 Oct 2024 09:24:40 +0200") References: <20241011063730.310568-1-shanmu1901@gmail.com> <20241011063730.310568-2-shanmu1901@gmail.com> User-Agent: mu4e 1.12.1; emacs 29.4 Date: Fri, 11 Oct 2024 09:41:01 +0200 Message-ID: <87zfnb84tu.fsf@xenomai.org> Precedence: bulk X-Mailing-List: xenomai@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain Florian Bezdeka writes: > On Fri, 2024-10-11 at 09:15 +0200, Jan Kiszka wrote: >> On 11.10.24 08:37, shannmu wrote: >> > This adds virtual interrupt functions `arch_xxx`, >> > irq-pipelined top-level interrupt handler `handle_riscv_irq` >> > and `handle_arch_irq_pipelined`, >> > real interrupt-flags functions `native_xxx`, >> > `mark_trap_entry` and `mark_trap_exit` in trap functions, >> > multiplexed ipi_message_type `IPI_RESCHEDULE` for in-band ipi. >> > >> > Signed-off-by: shannmu >> > --- >> > arch/riscv/Kconfig | 5 + >> > arch/riscv/include/asm/dovetail.h | 58 +++++++ >> > arch/riscv/include/asm/irq_pipeline.h | 173 +++++++++++++++++++++ >> > arch/riscv/include/asm/irqflags.h | 26 ++-- >> > arch/riscv/include/asm/mmu_context.h | 21 ++- >> > arch/riscv/include/asm/syscall.h | 6 + >> > arch/riscv/kernel/Makefile | 1 + >> > arch/riscv/kernel/irq.c | 72 ++++++--- >> > arch/riscv/kernel/irq_pipeline.c | 46 ++++++ >> > arch/riscv/kernel/smp.c | 135 ++++++++++++---- >> > arch/riscv/kernel/smpboot.c | 2 +- >> > arch/riscv/kernel/traps.c | 212 +++++++++++++++----------- >> > arch/riscv/mm/fault.c | 46 +++--- >> > 13 files changed, 633 insertions(+), 170 deletions(-) >> > create mode 100644 arch/riscv/include/asm/dovetail.h >> > create mode 100644 arch/riscv/include/asm/irq_pipeline.h >> > create mode 100644 arch/riscv/kernel/irq_pipeline.c >> > >> >> Thanks for sharing your work! Could you explain how these bits compare >> to what Tobias sent earlier [1]? Is it possible to combine your work >> with that to ensure nothing relevant is missed? > > Thanks for sharing +1. One major difference is the base branch. Tobias > was working on 6.11 while this one is based on 6.6. > > As we now have two different works streams it makes sense to > synchronize and ideally align on a roadmap / work sharing plan. That > would help to minimize review / testing efforts - at least on my side. > Agreed. For the record, I'm willing to merge the RISC-V architecture support into Dovetail and the EVL core. We'd just need to merge both ongoing efforts to get this done faster. -- Philippe.