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From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>,
	intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, mika.kahola@intel.com,
	matthew.d.roper@intel.com
Subject: Re: [PATCH 2/5] drm/i915/snps_phy: Use HDMI PLL algorithm for DG2
Date: Thu, 27 Jun 2024 21:30:41 +0300	[thread overview]
Message-ID: <87zfr6b5m6.fsf@intel.com> (raw)
In-Reply-To: <0d2f4cb3-c418-46c6-b0ca-8aa1650aeeff@intel.com>

On Thu, 27 Jun 2024, "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com> wrote:
> On 6/26/2024 3:37 PM, Jani Nikula wrote:
>> On Wed, 26 Jun 2024, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>>> Try SNPS_PHY HDMI tables computed using the algorithm, before using
>>> consolidated tables.
>>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/display/intel_snps_phy.c | 20 ++++++++-----------
>>>   1 file changed, 8 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>>> index e6df1f92def5..10fe28af0d11 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>>> @@ -12,6 +12,7 @@
>>>   #include "intel_display_types.h"
>>>   #include "intel_snps_phy.h"
>>>   #include "intel_snps_phy_regs.h"
>>> +#include "intel_pll_algorithm.h"
>> Keep includes sorted.
> Noted. Thanks for pointing this out.
>>
>>>   
>>>   /**
>>>    * DOC: Synopsis PHY support
>>> @@ -1787,22 +1788,14 @@ intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
>>>   int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
>>>   			   struct intel_encoder *encoder)
>>>   {
>>> -	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>>>   	const struct intel_mpllb_state * const *tables;
>>>   	int i;
>>>   
>>>   	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
>>> -		if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock)
>>> -		    != MODE_OK) {
>>> -			/*
>>> -			 * FIXME: Can only support fixed HDMI frequencies
>>> -			 * until we have a proper algorithm under a valid
>>> -			 * license.
>>> -			 */
>>> -			drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n",
>>> -				    crtc_state->port_clock);
>>> -			return -EINVAL;
>>> -		}
>>> +		/* try computed SNPS_PHY HDMI tables before using consolidated tables */
>> Computed tables vs. consolidated tables? Huh?
>>
>> Anyway, I think we have two choices here:
>>
>> - Always use computed values.
>>
>> - Prefer fixed tables, fall back to computed values.
>>
>> But we definitely should not try to compute first and fall back to fixed
>> tables.
>
> Hmm I was not sure if we need the fixed tables after this and whether we 
> should remove them altogether.
>
> But it makes more sense to use prefer the fixed tables and fall back to 
> computed values.
>
> I'll make the changes in the next version.
>
>
>>
>>> +		if (intel_snps_phy_compute_hdmi_tmds_pll(crtc_state->port_clock,
>>> +							 &crtc_state->dpll_hw_state.mpllb) == 0)
>>> +			return 0;
>>>   	}
>>>   
>>>   	tables = intel_mpllb_tables_get(crtc_state, encoder);
>>> @@ -1991,6 +1984,9 @@ int intel_snps_phy_check_hdmi_link_rate(int clock)
>>>   			return MODE_OK;
>>>   	}
>>>   
>>> +	if (clock >= 25175 && clock <= 594000)
>>> +		return MODE_OK;
>>> +
>> How's this related to the patch at hand?
>
> Currently we prune the modes if the clock does not match that given in 
> the table.
>
> Now that we support all clocks between 25175 and 594000 we need this, 
> but perhaps will add as a separate patch.
>
> Perhaps I can remove this function all together and put the condition in 
> hdmi_port_clock valid, in separate patch.

But we already have intel_hdmi_source_max_tmds_clock(), which also takes
into account platform specifics. For example the fact that 594000 is not
the max on all platforms.

BR,
Jani.





>
> Regards,
>
> Ankit
>
>
>>
>>>   	return MODE_CLOCK_RANGE;
>>>   }

-- 
Jani Nikula, Intel

  reply	other threads:[~2024-06-27 18:30 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-26  5:00 [PATCH 0/5] Add HDMI PLL Algorithm for SNPS/C10PHY Ankit Nautiyal
2024-06-26  5:00 ` [PATCH 1/5] drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2 Ankit Nautiyal
2024-06-26 10:04   ` Jani Nikula
2024-06-27 16:41     ` Nautiyal, Ankit K
2024-06-26 18:12   ` kernel test robot
2024-06-26 18:46   ` kernel test robot
2024-06-26  5:00 ` [PATCH 2/5] drm/i915/snps_phy: Use " Ankit Nautiyal
2024-06-26 10:07   ` Jani Nikula
2024-06-27 17:02     ` Nautiyal, Ankit K
2024-06-27 18:30       ` Jani Nikula [this message]
2024-06-28  5:06         ` Nautiyal, Ankit K
2024-06-26  5:00 ` [PATCH 3/5] drm/i915/cx0_phy_regs: Add C10 registers bits Ankit Nautiyal
2024-06-26  5:00 ` [PATCH 4/5] drm/i915/pll_algorithm: Compute C10 HDMI PLLs with algorithm Ankit Nautiyal
2024-06-26 10:10   ` Jani Nikula
2024-06-27 17:08     ` Nautiyal, Ankit K
2024-06-26  5:00 ` [PATCH 5/5] drm/xe: Add intel_pll_algorithm in Makefile Ankit Nautiyal
2024-06-26 10:12   ` Jani Nikula
2024-06-27 17:12     ` Nautiyal, Ankit K
2024-06-26  5:05 ` ✓ CI.Patch_applied: success for Add HDMI PLL Algorithm for SNPS/C10PHY Patchwork
2024-06-26  5:05 ` ✗ CI.checkpatch: warning " Patchwork
2024-06-26  5:06 ` ✓ CI.KUnit: success " Patchwork
2024-06-26  5:18 ` ✓ CI.Build: " Patchwork
2024-06-26  5:20 ` ✗ CI.Hooks: failure " Patchwork
2024-06-26  5:22 ` ✗ CI.checksparse: warning " Patchwork
2024-06-26  5:42 ` ✗ Fi.CI.CHECKPATCH: " Patchwork
2024-06-26  5:42 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-06-26  5:44 ` ✓ CI.BAT: success " Patchwork
2024-06-26  5:50 ` ✓ Fi.CI.BAT: " Patchwork
2024-06-26  7:06 ` ✓ CI.FULL: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2024-08-06 12:58 [PATCH 0/5] " Ankit Nautiyal
2024-08-06 12:58 ` [PATCH 2/5] drm/i915/snps_phy: Use HDMI PLL algorithm for DG2 Ankit Nautiyal
2024-08-13  3:19 [PATCH 0/5] Add HDMI PLL Algorithm for SNPS/C10PHY Ankit Nautiyal
2024-08-13  3:19 ` [PATCH 2/5] drm/i915/snps_phy: Use HDMI PLL algorithm for DG2 Ankit Nautiyal
2025-01-10  5:48   ` Kandpal, Suraj
2025-01-20  4:21 [PATCH 0/5] Add HDMI PLL Algorithm for SNPS/C10PHY Ankit Nautiyal
2025-01-20  4:21 ` [PATCH 2/5] drm/i915/snps_phy: Use HDMI PLL algorithm for DG2 Ankit Nautiyal

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