From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9BCA134BF for ; Thu, 19 Oct 2023 08:03:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QjFRoQHS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 11B9DC433C8; Thu, 19 Oct 2023 08:03:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1697702615; bh=LhSdq/c75J6zoqoAoEwSl7/CcFxNpbuye8xEYUwT5wI=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=QjFRoQHSJ5yO7Ek0U9zygFykYgp7SpupdWWGpEy3SUetWSRI5IGL8frR2NyPDn+ir rneMEeZU4n4GqHlfgPvpXk0u0BY96rDYHoatPzPk5Q4zkFPgo4NZudW9XvgFOujoUG hRHIwr6x18j7QORIHphHPluU06zkpE4b+Hm9mzC4z3t93L8jQY6FZQJ0zouNhTTG8M 0+VIgSHBZtkPwM4s3gmUpnWzZD+Gaz5B+ADlRjHA0dR36jgREjVHKVemj215q/ACDg nTDr7A9+iYoWJkdo0r4jaw4GzsTk+5hkrs+bQrwQBWqVOx0mnCnUnceUtcHnOFUIH1 4OloqZxxmnJIg== Received: from ip-185-104-136-29.ptr.icomera.net ([185.104.136.29] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qtO06-005exJ-6f; Thu, 19 Oct 2023 09:03:32 +0100 Date: Thu, 19 Oct 2023 09:03:05 +0100 Message-ID: <87zg0f59ae.wl-maz@kernel.org> From: Marc Zyngier To: Ryan Roberts Cc: Catalin Marinas , Will Deacon , Oliver Upton , Suzuki K Poulose , James Morse , Zenghui Yu , Ard Biesheuvel , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Subject: Re: [PATCH v4 01/12] arm64/mm: Update non-range tlb invalidation routines for FEAT_LPA2 In-Reply-To: <20231009185008.3803879-2-ryan.roberts@arm.com> References: <20231009185008.3803879-1-ryan.roberts@arm.com> <20231009185008.3803879-2-ryan.roberts@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.104.136.29 X-SA-Exim-Rcpt-To: ryan.roberts@arm.com, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, suzuki.poulose@arm.com, james.morse@arm.com, yuzenghui@huawei.com, ardb@kernel.org, anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 09 Oct 2023 19:49:57 +0100, Ryan Roberts wrote: > > FEAT_LPA2 impacts tlb invalidation in 2 ways; Firstly, the TTL field in > the non-range tlbi instructions can now validly take a 0 value for the > 4KB granule (this is due to the extra level of translation). Secondly, nit: 0 was always valid. It just didn't indicate any level. > the BADDR field in the range tlbi instructions must be aligned to 64KB > when LPA2 is in use (TCR.DS=1). Changes are required for tlbi to > continue to operate correctly when LPA2 is in use. > > KVM only uses the non-range (__tlbi_level()) routines. Therefore we only > solve the first problem with this patch. Is this still true? This patch changes __TLBI_VADDR_RANGE() and co. > > It is solved by always adding the level hint if the level is between [0, > 3] (previously anything other than 0 was hinted, which breaks in the new > level -1 case from kvm). When running on non-LPA2 HW, 0 is still safe to > hint as the HW will fall back to non-hinted. While we are at it, we > replace the notion of 0 being the non-hinted seninel with a macro, > TLBI_TTL_UNKNOWN. This means callers won't need updating if/when > translation depth increases in future. > > Signed-off-by: Ryan Roberts > Reviewed-by: Catalin Marinas > --- > arch/arm64/include/asm/tlb.h | 9 ++++--- > arch/arm64/include/asm/tlbflush.h | 43 +++++++++++++++++++------------ > 2 files changed, 31 insertions(+), 21 deletions(-) > > diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h > index 2c29239d05c3..93c537635dbb 100644 > --- a/arch/arm64/include/asm/tlb.h > +++ b/arch/arm64/include/asm/tlb.h > @@ -22,15 +22,16 @@ static void tlb_flush(struct mmu_gather *tlb); > #include > > /* > - * get the tlbi levels in arm64. Default value is 0 if more than one > - * of cleared_* is set or neither is set. > + * get the tlbi levels in arm64. Default value is TLBI_TTL_UNKNOWN if more than > + * one of cleared_* is set or neither is set - this elides the level hinting to > + * the hardware. > * Arm64 doesn't support p4ds now. > */ > static inline int tlb_get_level(struct mmu_gather *tlb) > { > /* The TTL field is only valid for the leaf entry. */ > if (tlb->freed_tables) > - return 0; > + return TLBI_TTL_UNKNOWN; > > if (tlb->cleared_ptes && !(tlb->cleared_pmds || > tlb->cleared_puds || > @@ -47,7 +48,7 @@ static inline int tlb_get_level(struct mmu_gather *tlb) > tlb->cleared_p4ds)) > return 1; > > - return 0; > + return TLBI_TTL_UNKNOWN; > } > > static inline void tlb_flush(struct mmu_gather *tlb) > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index b149cf9f91bc..e688246b3b13 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -94,19 +94,22 @@ static inline unsigned long get_trans_granule(void) > * When ARMv8.4-TTL exists, TLBI operations take an additional hint for > * the level at which the invalidation must take place. If the level is > * wrong, no invalidation may take place. In the case where the level > - * cannot be easily determined, a 0 value for the level parameter will > - * perform a non-hinted invalidation. > + * cannot be easily determined, the value TLBI_TTL_UNKNOWN will perform > + * a non-hinted invalidation. Any provided level outside the hint range > + * will also cause fall-back to non-hinted invalidation. > * > * For Stage-2 invalidation, use the level values provided to that effect > * in asm/stage2_pgtable.h. > */ > #define TLBI_TTL_MASK GENMASK_ULL(47, 44) > > +#define TLBI_TTL_UNKNOWN (-1) I find this value somehow confusing, as it represent an actual level number. It just happen to be one that cannot be provided as a TTL. So having that as a return value from tlb_get_level() isn't great, and I'd rather have something that cannot be mistaken for a valid level. > + > #define __tlbi_level(op, addr, level) do { \ > u64 arg = addr; \ > \ > if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \ > - level) { \ > + level >= 0 && level <= 3) { \ > u64 ttl = level & 3; \ > ttl |= get_trans_granule() << 2; \ > arg &= ~TLBI_TTL_MASK; \ > @@ -134,16 +137,17 @@ static inline unsigned long get_trans_granule(void) > * [BADDR, BADDR + (NUM + 1) * 2^(5*SCALE + 1) * PAGESIZE) > * > */ > -#define __TLBI_VADDR_RANGE(addr, asid, scale, num, ttl) \ > - ({ \ > - unsigned long __ta = (addr) >> PAGE_SHIFT; \ > - __ta &= GENMASK_ULL(36, 0); \ > - __ta |= (unsigned long)(ttl) << 37; \ > - __ta |= (unsigned long)(num) << 39; \ > - __ta |= (unsigned long)(scale) << 44; \ > - __ta |= get_trans_granule() << 46; \ > - __ta |= (unsigned long)(asid) << 48; \ > - __ta; \ > +#define __TLBI_VADDR_RANGE(addr, asid, scale, num, ttl) \ > + ({ \ > + unsigned long __ta = (addr) >> PAGE_SHIFT; \ > + unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \ > + __ta &= GENMASK_ULL(36, 0); \ > + __ta |= __ttl << 37; \ > + __ta |= (unsigned long)(num) << 39; \ > + __ta |= (unsigned long)(scale) << 44; \ > + __ta |= get_trans_granule() << 46; \ > + __ta |= (unsigned long)(asid) << 48; \ > + __ta; \ > }) > > /* These macros are used by the TLBI RANGE feature. */ > @@ -216,12 +220,16 @@ static inline unsigned long get_trans_granule(void) > * CPUs, ensuring that any walk-cache entries associated with the > * translation are also invalidated. > * > - * __flush_tlb_range(vma, start, end, stride, last_level) > + * __flush_tlb_range(vma, start, end, stride, last_level, tlb_level) > * Invalidate the virtual-address range '[start, end)' on all > * CPUs for the user address space corresponding to 'vma->mm'. > * The invalidation operations are issued at a granularity > * determined by 'stride' and only affect any walk-cache entries > - * if 'last_level' is equal to false. > + * if 'last_level' is equal to false. tlb_level is the level at > + * which the invalidation must take place. If the level is wrong, > + * no invalidation may take place. In the case where the level > + * cannot be easily determined, the value TLBI_TTL_UNKNOWN will > + * perform a non-hinted invalidation. > * > * > * Finally, take a look at asm/tlb.h to see how tlb_flush() is implemented > @@ -442,9 +450,10 @@ static inline void flush_tlb_range(struct vm_area_struct *vma, > /* > * We cannot use leaf-only invalidation here, since we may be invalidating > * table entries as part of collapsing hugepages or moving page tables. > - * Set the tlb_level to 0 because we can not get enough information here. > + * Set the tlb_level to TLBI_TTL_UNKNOWN because we can not get enough > + * information here. > */ > - __flush_tlb_range(vma, start, end, PAGE_SIZE, false, 0); > + __flush_tlb_range(vma, start, end, PAGE_SIZE, false, TLBI_TTL_UNKNOWN); > } > > static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) It feels like this range stuff would be better located in the second patch. Not a huge deal though. M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3EBB9CDB465 for ; Thu, 19 Oct 2023 08:04:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WNr8pRMfuOBMv6/2kMt8wK95J0swTJ+6ZMxZ3fEBfj0=; b=zYLqH7etK4Cgua mKSN86pWVEKVo8ibnEZNdQC8aZnk8S4z58j2Mx1ekPTk3cjZCewPudarYCw8ko101y2cCMqLsqLNU RLwDVI28QAeAxJp8hIXh1m2wdi3LcDAsa+lQqPdUd5vgsUhZPmB40K6EMZBVjjmTjk82mDVH4AGxX KE4RPgxezoVhEZQmqPWnNFVrwtvO3e4qSOjaMkLM/2+1YLQB9fLjifzB6C5+65TrVIC+lsoZXwJ49 /zF171GQnjiwjGMzFK7QQfmC8n1cl9fCxjjyMpzXXdnUOutfsINc3i5LKFIS7TK8PAyjz29eYAaxF Vrv9c7JiYe43xgnJMcVQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qtO0O-00GfMg-04; Thu, 19 Oct 2023 08:03:44 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qtO0K-00GfLL-2u for linux-arm-kernel@lists.infradead.org; Thu, 19 Oct 2023 08:03:42 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id F143FCE295C; Thu, 19 Oct 2023 08:03:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 11B9DC433C8; Thu, 19 Oct 2023 08:03:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1697702615; bh=LhSdq/c75J6zoqoAoEwSl7/CcFxNpbuye8xEYUwT5wI=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=QjFRoQHSJ5yO7Ek0U9zygFykYgp7SpupdWWGpEy3SUetWSRI5IGL8frR2NyPDn+ir rneMEeZU4n4GqHlfgPvpXk0u0BY96rDYHoatPzPk5Q4zkFPgo4NZudW9XvgFOujoUG hRHIwr6x18j7QORIHphHPluU06zkpE4b+Hm9mzC4z3t93L8jQY6FZQJ0zouNhTTG8M 0+VIgSHBZtkPwM4s3gmUpnWzZD+Gaz5B+ADlRjHA0dR36jgREjVHKVemj215q/ACDg nTDr7A9+iYoWJkdo0r4jaw4GzsTk+5hkrs+bQrwQBWqVOx0mnCnUnceUtcHnOFUIH1 4OloqZxxmnJIg== Received: from ip-185-104-136-29.ptr.icomera.net ([185.104.136.29] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qtO06-005exJ-6f; Thu, 19 Oct 2023 09:03:32 +0100 Date: Thu, 19 Oct 2023 09:03:05 +0100 Message-ID: <87zg0f59ae.wl-maz@kernel.org> From: Marc Zyngier To: Ryan Roberts Cc: Catalin Marinas , Will Deacon , Oliver Upton , Suzuki K Poulose , James Morse , Zenghui Yu , Ard Biesheuvel , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Subject: Re: [PATCH v4 01/12] arm64/mm: Update non-range tlb invalidation routines for FEAT_LPA2 In-Reply-To: <20231009185008.3803879-2-ryan.roberts@arm.com> References: <20231009185008.3803879-1-ryan.roberts@arm.com> <20231009185008.3803879-2-ryan.roberts@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.104.136.29 X-SA-Exim-Rcpt-To: ryan.roberts@arm.com, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, suzuki.poulose@arm.com, james.morse@arm.com, yuzenghui@huawei.com, ardb@kernel.org, anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231019_010341_282028_F4DB3076 X-CRM114-Status: GOOD ( 46.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 09 Oct 2023 19:49:57 +0100, Ryan Roberts wrote: > > FEAT_LPA2 impacts tlb invalidation in 2 ways; Firstly, the TTL field in > the non-range tlbi instructions can now validly take a 0 value for the > 4KB granule (this is due to the extra level of translation). Secondly, nit: 0 was always valid. It just didn't indicate any level. > the BADDR field in the range tlbi instructions must be aligned to 64KB > when LPA2 is in use (TCR.DS=1). Changes are required for tlbi to > continue to operate correctly when LPA2 is in use. > > KVM only uses the non-range (__tlbi_level()) routines. Therefore we only > solve the first problem with this patch. Is this still true? This patch changes __TLBI_VADDR_RANGE() and co. > > It is solved by always adding the level hint if the level is between [0, > 3] (previously anything other than 0 was hinted, which breaks in the new > level -1 case from kvm). When running on non-LPA2 HW, 0 is still safe to > hint as the HW will fall back to non-hinted. While we are at it, we > replace the notion of 0 being the non-hinted seninel with a macro, > TLBI_TTL_UNKNOWN. This means callers won't need updating if/when > translation depth increases in future. > > Signed-off-by: Ryan Roberts > Reviewed-by: Catalin Marinas > --- > arch/arm64/include/asm/tlb.h | 9 ++++--- > arch/arm64/include/asm/tlbflush.h | 43 +++++++++++++++++++------------ > 2 files changed, 31 insertions(+), 21 deletions(-) > > diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h > index 2c29239d05c3..93c537635dbb 100644 > --- a/arch/arm64/include/asm/tlb.h > +++ b/arch/arm64/include/asm/tlb.h > @@ -22,15 +22,16 @@ static void tlb_flush(struct mmu_gather *tlb); > #include > > /* > - * get the tlbi levels in arm64. Default value is 0 if more than one > - * of cleared_* is set or neither is set. > + * get the tlbi levels in arm64. Default value is TLBI_TTL_UNKNOWN if more than > + * one of cleared_* is set or neither is set - this elides the level hinting to > + * the hardware. > * Arm64 doesn't support p4ds now. > */ > static inline int tlb_get_level(struct mmu_gather *tlb) > { > /* The TTL field is only valid for the leaf entry. */ > if (tlb->freed_tables) > - return 0; > + return TLBI_TTL_UNKNOWN; > > if (tlb->cleared_ptes && !(tlb->cleared_pmds || > tlb->cleared_puds || > @@ -47,7 +48,7 @@ static inline int tlb_get_level(struct mmu_gather *tlb) > tlb->cleared_p4ds)) > return 1; > > - return 0; > + return TLBI_TTL_UNKNOWN; > } > > static inline void tlb_flush(struct mmu_gather *tlb) > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index b149cf9f91bc..e688246b3b13 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -94,19 +94,22 @@ static inline unsigned long get_trans_granule(void) > * When ARMv8.4-TTL exists, TLBI operations take an additional hint for > * the level at which the invalidation must take place. If the level is > * wrong, no invalidation may take place. In the case where the level > - * cannot be easily determined, a 0 value for the level parameter will > - * perform a non-hinted invalidation. > + * cannot be easily determined, the value TLBI_TTL_UNKNOWN will perform > + * a non-hinted invalidation. Any provided level outside the hint range > + * will also cause fall-back to non-hinted invalidation. > * > * For Stage-2 invalidation, use the level values provided to that effect > * in asm/stage2_pgtable.h. > */ > #define TLBI_TTL_MASK GENMASK_ULL(47, 44) > > +#define TLBI_TTL_UNKNOWN (-1) I find this value somehow confusing, as it represent an actual level number. It just happen to be one that cannot be provided as a TTL. So having that as a return value from tlb_get_level() isn't great, and I'd rather have something that cannot be mistaken for a valid level. > + > #define __tlbi_level(op, addr, level) do { \ > u64 arg = addr; \ > \ > if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \ > - level) { \ > + level >= 0 && level <= 3) { \ > u64 ttl = level & 3; \ > ttl |= get_trans_granule() << 2; \ > arg &= ~TLBI_TTL_MASK; \ > @@ -134,16 +137,17 @@ static inline unsigned long get_trans_granule(void) > * [BADDR, BADDR + (NUM + 1) * 2^(5*SCALE + 1) * PAGESIZE) > * > */ > -#define __TLBI_VADDR_RANGE(addr, asid, scale, num, ttl) \ > - ({ \ > - unsigned long __ta = (addr) >> PAGE_SHIFT; \ > - __ta &= GENMASK_ULL(36, 0); \ > - __ta |= (unsigned long)(ttl) << 37; \ > - __ta |= (unsigned long)(num) << 39; \ > - __ta |= (unsigned long)(scale) << 44; \ > - __ta |= get_trans_granule() << 46; \ > - __ta |= (unsigned long)(asid) << 48; \ > - __ta; \ > +#define __TLBI_VADDR_RANGE(addr, asid, scale, num, ttl) \ > + ({ \ > + unsigned long __ta = (addr) >> PAGE_SHIFT; \ > + unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \ > + __ta &= GENMASK_ULL(36, 0); \ > + __ta |= __ttl << 37; \ > + __ta |= (unsigned long)(num) << 39; \ > + __ta |= (unsigned long)(scale) << 44; \ > + __ta |= get_trans_granule() << 46; \ > + __ta |= (unsigned long)(asid) << 48; \ > + __ta; \ > }) > > /* These macros are used by the TLBI RANGE feature. */ > @@ -216,12 +220,16 @@ static inline unsigned long get_trans_granule(void) > * CPUs, ensuring that any walk-cache entries associated with the > * translation are also invalidated. > * > - * __flush_tlb_range(vma, start, end, stride, last_level) > + * __flush_tlb_range(vma, start, end, stride, last_level, tlb_level) > * Invalidate the virtual-address range '[start, end)' on all > * CPUs for the user address space corresponding to 'vma->mm'. > * The invalidation operations are issued at a granularity > * determined by 'stride' and only affect any walk-cache entries > - * if 'last_level' is equal to false. > + * if 'last_level' is equal to false. tlb_level is the level at > + * which the invalidation must take place. If the level is wrong, > + * no invalidation may take place. In the case where the level > + * cannot be easily determined, the value TLBI_TTL_UNKNOWN will > + * perform a non-hinted invalidation. > * > * > * Finally, take a look at asm/tlb.h to see how tlb_flush() is implemented > @@ -442,9 +450,10 @@ static inline void flush_tlb_range(struct vm_area_struct *vma, > /* > * We cannot use leaf-only invalidation here, since we may be invalidating > * table entries as part of collapsing hugepages or moving page tables. > - * Set the tlb_level to 0 because we can not get enough information here. > + * Set the tlb_level to TLBI_TTL_UNKNOWN because we can not get enough > + * information here. > */ > - __flush_tlb_range(vma, start, end, PAGE_SIZE, false, 0); > + __flush_tlb_range(vma, start, end, PAGE_SIZE, false, TLBI_TTL_UNKNOWN); > } > > static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) It feels like this range stuff would be better located in the second patch. Not a huge deal though. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel