diff for duplicates of <87zii8tydd.fsf@free-electrons.com> diff --git a/a/1.txt b/N1/1.txt index 57b7b08..d19a62a 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,13 +1,13 @@ Hi Chris, - On lun., janv. 30 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: + On lun., janv. 30 2017, Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org> wrote: > The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs > with integrated CPUs. They are similar to the Armada XP SoCs but have > different I/O interfaces. > -> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> -> Acked-by: Rob Herring <robh@kernel.org> +> Signed-off-by: Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org> +> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> Applied on mvebu/dt @@ -105,7 +105,7 @@ Gregory > + #size-cells = <1>; > + ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; > + -> + packet-processor at 0 { +> + packet-processor@0 { > + compatible = "marvell,prestera-98dx3236"; > + reg = <0 0x4000000>; > + interrupts = <33>, <34>, <35>; @@ -128,7 +128,7 @@ Gregory > + #size-cells = <1>; > + ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; > + -> + dfx: dfx at 0 { +> + dfx: dfx@0 { > + compatible = "marvell,dfx-server"; > + reg = <0 0x100000>; > + }; @@ -203,7 +203,7 @@ Gregory > + #size-cells = <0>; > + enable-method = "marvell,98dx3236-smp"; > + -> + cpu at 0 { +> + cpu@0 { > + device_type = "cpu"; > + compatible = "marvell,sheeva-v7"; > + reg = <0>; @@ -222,7 +222,7 @@ Gregory > + /* > + * 98DX3236 has 1 x1 PCIe unit Gen2.0 > + */ -> + pciec: pcie-controller at 82000000 { +> + pciec: pcie-controller@82000000 { > + compatible = "marvell,armada-xp-pcie"; > + status = "disabled"; > + device_type = "pci"; @@ -239,7 +239,7 @@ Gregory > + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ > + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>; > + -> + pcie1: pcie at 1,0 { +> + pcie1: pcie@1,0 { > + device_type = "pci"; > + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; > + reg = <0x0800 0 0 0 0>; @@ -258,31 +258,31 @@ Gregory > + }; > + > + internal-regs { -> + coreclk: mvebu-sar at 18230 { +> + coreclk: mvebu-sar@18230 { > + compatible = "marvell,mv98dx3236-core-clock"; > + }; > + -> + cpuclk: clock-complex at 18700 { +> + cpuclk: clock-complex@18700 { > + compatible = "marvell,mv98dx3236-cpu-clock"; > + }; > + -> + corediv-clock at 18740 { +> + corediv-clock@18740 { > + status = "disabled"; > + }; > + -> + xor at 60900 { +> + xor@60900 { > + status = "disabled"; > + }; > + -> + crypto at 90000 { +> + crypto@90000 { > + status = "disabled"; > + }; > + -> + xor at f0900 { +> + xor@f0900 { > + status = "disabled"; > + }; > + -> + xor at f0800 { +> + xor@f0800 { > + compatible = "marvell,orion-xor"; > + reg = <0xf0800 0x100 > + 0xf0a00 0x100>; @@ -302,7 +302,7 @@ Gregory > + }; > + }; > + -> + gpio0: gpio at 18100 { +> + gpio0: gpio@18100 { > + compatible = "marvell,orion-gpio"; > + reg = <0x18100 0x40>; > + ngpios = <32>; @@ -314,13 +314,13 @@ Gregory > + }; > + > + /* does not exist */ -> + gpio1: gpio at 18140 { +> + gpio1: gpio@18140 { > + compatible = "marvell,orion-gpio"; > + reg = <0x18140 0x40>; > + status = "disabled"; > + }; > + -> + gpio2: gpio at 18180 { /* rework some properties */ +> + gpio2: gpio@18180 { /* rework some properties */ > + compatible = "marvell,orion-gpio"; > + reg = <0x18180 0x40>; > + ngpios = <1>; /* only gpio #32 */ @@ -331,18 +331,18 @@ Gregory > + interrupts = <87>; > + }; > + -> + nand: nand at d0000 { +> + nand: nand@d0000 { > + clocks = <&dfx_coredivclk 0>; > + }; > + }; > + -> + dfxr: dfx-registers at ac000000 { +> + dfxr: dfx-registers@ac000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; > + -> + dfx_coredivclk: corediv-clock at f8268 { +> + dfx_coredivclk: corediv-clock@f8268 { > + compatible = "marvell,mv98dx3236-corediv-clock"; > + reg = <0xf8268 0xc>; > + #clock-cells = <1>; @@ -350,19 +350,19 @@ Gregory > + clock-output-names = "nand"; > + }; > + -> + dfx: dfx at 0 { +> + dfx: dfx@0 { > + compatible = "marvell,dfx-server"; > + reg = <0 0x100000>; > + }; > + }; > + -> + switch: switch at a8000000 { +> + switch: switch@a8000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; > + -> + pp0: packet-processor at 0 { +> + pp0: packet-processor@0 { > + compatible = "marvell,prestera-98dx3236"; > + reg = <0 0x4000000>; > + interrupts = <33>, <34>, <35>; @@ -453,7 +453,7 @@ Gregory > + compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp"; > + > + cpus { -> + cpu at 1 { +> + cpu@1 { > + device_type = "cpu"; > + compatible = "marvell,sheeva-v7"; > + reg = <1>; @@ -464,7 +464,7 @@ Gregory > + > + soc { > + internal-regs { -> + resume at 20980 { +> + resume@20980 { > + compatible = "marvell,98dx3336-resume-ctrl"; > + reg = <0x20980 0x10>; > + }; @@ -535,7 +535,7 @@ Gregory > + compatible = "marvell,armadaxp-98dx4521", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp"; > + > + cpus { -> + cpu at 1 { +> + cpu@1 { > + device_type = "cpu"; > + compatible = "marvell,sheeva-v7"; > + reg = <1>; @@ -546,7 +546,7 @@ Gregory > + > + soc { > + internal-regs { -> + resume at 20980 { +> + resume@20980 { > + compatible = "marvell,98dx3336-resume-ctrl"; > + reg = <0x20980 0x10>; > + }; @@ -580,3 +580,7 @@ Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 57248f3..888b5aa 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,21 +1,32 @@ "ref\020170129232035.25189-1-chris.packham@alliedtelesis.co.nz\0" "ref\020170129232035.25189-5-chris.packham@alliedtelesis.co.nz\0" - "From\0gregory.clement@free-electrons.com (Gregory CLEMENT)\0" - "Subject\0[PATCH v6 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs\0" + "ref\020170129232035.25189-5-chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org\0" + "From\0Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" + "Subject\0Re: [PATCH v6 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs\0" "Date\0Mon, 30 Jan 2017 15:29:18 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>\0" + "Cc\0linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org" + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org> + Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org> + Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "Hi Chris,\n" " \n" - " On lun., janv. 30 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:\n" + " On lun., janv. 30 2017, Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org> wrote:\n" "\n" "> The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs\n" "> with integrated CPUs. They are similar to the Armada XP SoCs but have\n" "> different I/O interfaces.\n" ">\n" - "> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>\n" - "> Acked-by: Rob Herring <robh@kernel.org>\n" + "> Signed-off-by: Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>\n" + "> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\n" "\n" "Applied on mvebu/dt\n" "\n" @@ -113,7 +124,7 @@ "> +\t#size-cells = <1>;\n" "> +\tranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;\n" "> +\n" - "> +\tpacket-processor at 0 {\n" + "> +\tpacket-processor@0 {\n" "> +\t\tcompatible = \"marvell,prestera-98dx3236\";\n" "> +\t\treg = <0 0x4000000>;\n" "> +\t\tinterrupts = <33>, <34>, <35>;\n" @@ -136,7 +147,7 @@ "> +\t#size-cells = <1>;\n" "> +\tranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;\n" "> +\n" - "> +\tdfx: dfx at 0 {\n" + "> +\tdfx: dfx@0 {\n" "> +\t\tcompatible = \"marvell,dfx-server\";\n" "> +\t\treg = <0 0x100000>;\n" "> +\t};\n" @@ -211,7 +222,7 @@ "> +\t\t#size-cells = <0>;\n" "> +\t\tenable-method = \"marvell,98dx3236-smp\";\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"marvell,sheeva-v7\";\n" "> +\t\t\treg = <0>;\n" @@ -230,7 +241,7 @@ "> +\t\t/*\n" "> +\t\t * 98DX3236 has 1 x1 PCIe unit Gen2.0\n" "> +\t\t */\n" - "> +\t\tpciec: pcie-controller at 82000000 {\n" + "> +\t\tpciec: pcie-controller@82000000 {\n" "> +\t\t\tcompatible = \"marvell,armada-xp-pcie\";\n" "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t\tdevice_type = \"pci\";\n" @@ -247,7 +258,7 @@ "> +\t\t\t\t0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */\n" "> +\t\t\t\t0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;\n" "> +\n" - "> +\t\t\tpcie1: pcie at 1,0 {\n" + "> +\t\t\tpcie1: pcie@1,0 {\n" "> +\t\t\t\tdevice_type = \"pci\";\n" "> +\t\t\t\tassigned-addresses = <0x82000800 0 0x40000 0 0x2000>;\n" "> +\t\t\t\treg = <0x0800 0 0 0 0>;\n" @@ -266,31 +277,31 @@ "> +\t\t};\n" "> +\n" "> +\t\tinternal-regs {\n" - "> +\t\t\tcoreclk: mvebu-sar at 18230 {\n" + "> +\t\t\tcoreclk: mvebu-sar@18230 {\n" "> +\t\t\t\tcompatible = \"marvell,mv98dx3236-core-clock\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tcpuclk: clock-complex at 18700 {\n" + "> +\t\t\tcpuclk: clock-complex@18700 {\n" "> +\t\t\t\tcompatible = \"marvell,mv98dx3236-cpu-clock\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tcorediv-clock at 18740 {\n" + "> +\t\t\tcorediv-clock@18740 {\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\txor at 60900 {\n" + "> +\t\t\txor@60900 {\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tcrypto at 90000 {\n" + "> +\t\t\tcrypto@90000 {\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\txor at f0900 {\n" + "> +\t\t\txor@f0900 {\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\txor at f0800 {\n" + "> +\t\t\txor@f0800 {\n" "> +\t\t\t\tcompatible = \"marvell,orion-xor\";\n" "> +\t\t\t\treg = <0xf0800 0x100\n" "> +\t\t\t\t 0xf0a00 0x100>;\n" @@ -310,7 +321,7 @@ "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tgpio0: gpio at 18100 {\n" + "> +\t\t\tgpio0: gpio@18100 {\n" "> +\t\t\t\tcompatible = \"marvell,orion-gpio\";\n" "> +\t\t\t\treg = <0x18100 0x40>;\n" "> +\t\t\t\tngpios = <32>;\n" @@ -322,13 +333,13 @@ "> +\t\t\t};\n" "> +\n" "> +\t\t\t/* does not exist */\n" - "> +\t\t\tgpio1: gpio at 18140 {\n" + "> +\t\t\tgpio1: gpio@18140 {\n" "> +\t\t\t\tcompatible = \"marvell,orion-gpio\";\n" "> +\t\t\t\treg = <0x18140 0x40>;\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tgpio2: gpio at 18180 { /* rework some properties */\n" + "> +\t\t\tgpio2: gpio@18180 { /* rework some properties */\n" "> +\t\t\t\tcompatible = \"marvell,orion-gpio\";\n" "> +\t\t\t\treg = <0x18180 0x40>;\n" "> +\t\t\t\tngpios = <1>; /* only gpio #32 */\n" @@ -339,18 +350,18 @@ "> +\t\t\t\tinterrupts = <87>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tnand: nand at d0000 {\n" + "> +\t\t\tnand: nand@d0000 {\n" "> +\t\t\t\tclocks = <&dfx_coredivclk 0>;\n" "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tdfxr: dfx-registers at ac000000 {\n" + "> +\t\tdfxr: dfx-registers@ac000000 {\n" "> +\t\t\tcompatible = \"simple-bus\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;\n" "> +\n" - "> + dfx_coredivclk: corediv-clock at f8268 {\n" + "> + dfx_coredivclk: corediv-clock@f8268 {\n" "> + compatible = \"marvell,mv98dx3236-corediv-clock\";\n" "> + reg = <0xf8268 0xc>;\n" "> + #clock-cells = <1>;\n" @@ -358,19 +369,19 @@ "> + clock-output-names = \"nand\";\n" "> + };\n" "> +\n" - "> +\t\t\tdfx: dfx at 0 {\n" + "> +\t\t\tdfx: dfx@0 {\n" "> +\t\t\t\tcompatible = \"marvell,dfx-server\";\n" "> +\t\t\t\treg = <0 0x100000>;\n" "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tswitch: switch at a8000000 {\n" + "> +\t\tswitch: switch@a8000000 {\n" "> +\t\t\tcompatible = \"simple-bus\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;\n" "> +\n" - "> +\t\t\tpp0: packet-processor at 0 {\n" + "> +\t\t\tpp0: packet-processor@0 {\n" "> +\t\t\t\tcompatible = \"marvell,prestera-98dx3236\";\n" "> +\t\t\t\treg = <0 0x4000000>;\n" "> +\t\t\t\tinterrupts = <33>, <34>, <35>;\n" @@ -461,7 +472,7 @@ "> +\tcompatible = \"marvell,armadaxp-98dx3336\", \"marvell,armadaxp-98dx3236\", \"marvell,armadaxp\", \"marvell,armada-370-xp\";\n" "> +\n" "> +\tcpus {\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"marvell,sheeva-v7\";\n" "> +\t\t\treg = <1>;\n" @@ -472,7 +483,7 @@ "> +\n" "> +\tsoc {\n" "> +\t\tinternal-regs {\n" - "> +\t\t\tresume at 20980 {\n" + "> +\t\t\tresume@20980 {\n" "> +\t\t\t\tcompatible = \"marvell,98dx3336-resume-ctrl\";\n" "> +\t\t\t\treg = <0x20980 0x10>;\n" "> +\t\t\t};\n" @@ -543,7 +554,7 @@ "> +\tcompatible = \"marvell,armadaxp-98dx4521\", \"marvell,armadaxp-98dx3236\", \"marvell,armadaxp\", \"marvell,armada-370-xp\";\n" "> +\n" "> +\tcpus {\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"marvell,sheeva-v7\";\n" "> +\t\t\treg = <1>;\n" @@ -554,7 +565,7 @@ "> +\n" "> +\tsoc {\n" "> +\t\tinternal-regs {\n" - "> +\t\t\tresume at 20980 {\n" + "> +\t\t\tresume@20980 {\n" "> +\t\t\t\tcompatible = \"marvell,98dx3336-resume-ctrl\";\n" "> +\t\t\t\treg = <0x20980 0x10>;\n" "> +\t\t\t};\n" @@ -587,6 +598,10 @@ "Gregory Clement, Free Electrons\n" "Kernel, drivers, real-time and embedded Linux\n" "development, consulting, training and support.\n" - http://free-electrons.com + "http://free-electrons.com\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -28b70cbfbabe724c5d877d750d19bca08448b5521c032b8dcc912a2e4f0c66b6 +f5508765d29641f1d1f3eef9011e61ae2eea034a27afd5c47d84e8d7860f766d
diff --git a/a/1.txt b/N2/1.txt index 57b7b08..a8da670 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -105,7 +105,7 @@ Gregory > + #size-cells = <1>; > + ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; > + -> + packet-processor at 0 { +> + packet-processor@0 { > + compatible = "marvell,prestera-98dx3236"; > + reg = <0 0x4000000>; > + interrupts = <33>, <34>, <35>; @@ -128,7 +128,7 @@ Gregory > + #size-cells = <1>; > + ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; > + -> + dfx: dfx at 0 { +> + dfx: dfx@0 { > + compatible = "marvell,dfx-server"; > + reg = <0 0x100000>; > + }; @@ -203,7 +203,7 @@ Gregory > + #size-cells = <0>; > + enable-method = "marvell,98dx3236-smp"; > + -> + cpu at 0 { +> + cpu@0 { > + device_type = "cpu"; > + compatible = "marvell,sheeva-v7"; > + reg = <0>; @@ -222,7 +222,7 @@ Gregory > + /* > + * 98DX3236 has 1 x1 PCIe unit Gen2.0 > + */ -> + pciec: pcie-controller at 82000000 { +> + pciec: pcie-controller@82000000 { > + compatible = "marvell,armada-xp-pcie"; > + status = "disabled"; > + device_type = "pci"; @@ -239,7 +239,7 @@ Gregory > + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ > + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>; > + -> + pcie1: pcie at 1,0 { +> + pcie1: pcie@1,0 { > + device_type = "pci"; > + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; > + reg = <0x0800 0 0 0 0>; @@ -258,31 +258,31 @@ Gregory > + }; > + > + internal-regs { -> + coreclk: mvebu-sar at 18230 { +> + coreclk: mvebu-sar@18230 { > + compatible = "marvell,mv98dx3236-core-clock"; > + }; > + -> + cpuclk: clock-complex at 18700 { +> + cpuclk: clock-complex@18700 { > + compatible = "marvell,mv98dx3236-cpu-clock"; > + }; > + -> + corediv-clock at 18740 { +> + corediv-clock@18740 { > + status = "disabled"; > + }; > + -> + xor at 60900 { +> + xor@60900 { > + status = "disabled"; > + }; > + -> + crypto at 90000 { +> + crypto@90000 { > + status = "disabled"; > + }; > + -> + xor at f0900 { +> + xor@f0900 { > + status = "disabled"; > + }; > + -> + xor at f0800 { +> + xor@f0800 { > + compatible = "marvell,orion-xor"; > + reg = <0xf0800 0x100 > + 0xf0a00 0x100>; @@ -302,7 +302,7 @@ Gregory > + }; > + }; > + -> + gpio0: gpio at 18100 { +> + gpio0: gpio@18100 { > + compatible = "marvell,orion-gpio"; > + reg = <0x18100 0x40>; > + ngpios = <32>; @@ -314,13 +314,13 @@ Gregory > + }; > + > + /* does not exist */ -> + gpio1: gpio at 18140 { +> + gpio1: gpio@18140 { > + compatible = "marvell,orion-gpio"; > + reg = <0x18140 0x40>; > + status = "disabled"; > + }; > + -> + gpio2: gpio at 18180 { /* rework some properties */ +> + gpio2: gpio@18180 { /* rework some properties */ > + compatible = "marvell,orion-gpio"; > + reg = <0x18180 0x40>; > + ngpios = <1>; /* only gpio #32 */ @@ -331,18 +331,18 @@ Gregory > + interrupts = <87>; > + }; > + -> + nand: nand at d0000 { +> + nand: nand@d0000 { > + clocks = <&dfx_coredivclk 0>; > + }; > + }; > + -> + dfxr: dfx-registers at ac000000 { +> + dfxr: dfx-registers@ac000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; > + -> + dfx_coredivclk: corediv-clock at f8268 { +> + dfx_coredivclk: corediv-clock@f8268 { > + compatible = "marvell,mv98dx3236-corediv-clock"; > + reg = <0xf8268 0xc>; > + #clock-cells = <1>; @@ -350,19 +350,19 @@ Gregory > + clock-output-names = "nand"; > + }; > + -> + dfx: dfx at 0 { +> + dfx: dfx@0 { > + compatible = "marvell,dfx-server"; > + reg = <0 0x100000>; > + }; > + }; > + -> + switch: switch at a8000000 { +> + switch: switch@a8000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; > + -> + pp0: packet-processor at 0 { +> + pp0: packet-processor@0 { > + compatible = "marvell,prestera-98dx3236"; > + reg = <0 0x4000000>; > + interrupts = <33>, <34>, <35>; @@ -453,7 +453,7 @@ Gregory > + compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp"; > + > + cpus { -> + cpu at 1 { +> + cpu@1 { > + device_type = "cpu"; > + compatible = "marvell,sheeva-v7"; > + reg = <1>; @@ -464,7 +464,7 @@ Gregory > + > + soc { > + internal-regs { -> + resume at 20980 { +> + resume@20980 { > + compatible = "marvell,98dx3336-resume-ctrl"; > + reg = <0x20980 0x10>; > + }; @@ -535,7 +535,7 @@ Gregory > + compatible = "marvell,armadaxp-98dx4521", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp"; > + > + cpus { -> + cpu at 1 { +> + cpu@1 { > + device_type = "cpu"; > + compatible = "marvell,sheeva-v7"; > + reg = <1>; @@ -546,7 +546,7 @@ Gregory > + > + soc { > + internal-regs { -> + resume at 20980 { +> + resume@20980 { > + compatible = "marvell,98dx3336-resume-ctrl"; > + reg = <0x20980 0x10>; > + }; diff --git a/a/content_digest b/N2/content_digest index 57248f3..c4309bc 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,9 +1,19 @@ "ref\020170129232035.25189-1-chris.packham@alliedtelesis.co.nz\0" "ref\020170129232035.25189-5-chris.packham@alliedtelesis.co.nz\0" - "From\0gregory.clement@free-electrons.com (Gregory CLEMENT)\0" - "Subject\0[PATCH v6 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs\0" + "From\0Gregory CLEMENT <gregory.clement@free-electrons.com>\0" + "Subject\0Re: [PATCH v6 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs\0" "Date\0Mon, 30 Jan 2017 15:29:18 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Chris Packham <chris.packham@alliedtelesis.co.nz>\0" + "Cc\0linux@armlinux.org.uk" + linux-arm-kernel@lists.infradead.org + Rob Herring <robh+dt@kernel.org> + Mark Rutland <mark.rutland@arm.com> + Jason Cooper <jason@lakedaemon.net> + Andrew Lunn <andrew@lunn.ch> + Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + devicetree@vger.kernel.org + linux-kernel@vger.kernel.org + " netdev@vger.kernel.org\0" "\00:1\0" "b\0" "Hi Chris,\n" @@ -113,7 +123,7 @@ "> +\t#size-cells = <1>;\n" "> +\tranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;\n" "> +\n" - "> +\tpacket-processor at 0 {\n" + "> +\tpacket-processor@0 {\n" "> +\t\tcompatible = \"marvell,prestera-98dx3236\";\n" "> +\t\treg = <0 0x4000000>;\n" "> +\t\tinterrupts = <33>, <34>, <35>;\n" @@ -136,7 +146,7 @@ "> +\t#size-cells = <1>;\n" "> +\tranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;\n" "> +\n" - "> +\tdfx: dfx at 0 {\n" + "> +\tdfx: dfx@0 {\n" "> +\t\tcompatible = \"marvell,dfx-server\";\n" "> +\t\treg = <0 0x100000>;\n" "> +\t};\n" @@ -211,7 +221,7 @@ "> +\t\t#size-cells = <0>;\n" "> +\t\tenable-method = \"marvell,98dx3236-smp\";\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"marvell,sheeva-v7\";\n" "> +\t\t\treg = <0>;\n" @@ -230,7 +240,7 @@ "> +\t\t/*\n" "> +\t\t * 98DX3236 has 1 x1 PCIe unit Gen2.0\n" "> +\t\t */\n" - "> +\t\tpciec: pcie-controller at 82000000 {\n" + "> +\t\tpciec: pcie-controller@82000000 {\n" "> +\t\t\tcompatible = \"marvell,armada-xp-pcie\";\n" "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t\tdevice_type = \"pci\";\n" @@ -247,7 +257,7 @@ "> +\t\t\t\t0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */\n" "> +\t\t\t\t0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;\n" "> +\n" - "> +\t\t\tpcie1: pcie at 1,0 {\n" + "> +\t\t\tpcie1: pcie@1,0 {\n" "> +\t\t\t\tdevice_type = \"pci\";\n" "> +\t\t\t\tassigned-addresses = <0x82000800 0 0x40000 0 0x2000>;\n" "> +\t\t\t\treg = <0x0800 0 0 0 0>;\n" @@ -266,31 +276,31 @@ "> +\t\t};\n" "> +\n" "> +\t\tinternal-regs {\n" - "> +\t\t\tcoreclk: mvebu-sar at 18230 {\n" + "> +\t\t\tcoreclk: mvebu-sar@18230 {\n" "> +\t\t\t\tcompatible = \"marvell,mv98dx3236-core-clock\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tcpuclk: clock-complex at 18700 {\n" + "> +\t\t\tcpuclk: clock-complex@18700 {\n" "> +\t\t\t\tcompatible = \"marvell,mv98dx3236-cpu-clock\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tcorediv-clock at 18740 {\n" + "> +\t\t\tcorediv-clock@18740 {\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\txor at 60900 {\n" + "> +\t\t\txor@60900 {\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tcrypto at 90000 {\n" + "> +\t\t\tcrypto@90000 {\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\txor at f0900 {\n" + "> +\t\t\txor@f0900 {\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\txor at f0800 {\n" + "> +\t\t\txor@f0800 {\n" "> +\t\t\t\tcompatible = \"marvell,orion-xor\";\n" "> +\t\t\t\treg = <0xf0800 0x100\n" "> +\t\t\t\t 0xf0a00 0x100>;\n" @@ -310,7 +320,7 @@ "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tgpio0: gpio at 18100 {\n" + "> +\t\t\tgpio0: gpio@18100 {\n" "> +\t\t\t\tcompatible = \"marvell,orion-gpio\";\n" "> +\t\t\t\treg = <0x18100 0x40>;\n" "> +\t\t\t\tngpios = <32>;\n" @@ -322,13 +332,13 @@ "> +\t\t\t};\n" "> +\n" "> +\t\t\t/* does not exist */\n" - "> +\t\t\tgpio1: gpio at 18140 {\n" + "> +\t\t\tgpio1: gpio@18140 {\n" "> +\t\t\t\tcompatible = \"marvell,orion-gpio\";\n" "> +\t\t\t\treg = <0x18140 0x40>;\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tgpio2: gpio at 18180 { /* rework some properties */\n" + "> +\t\t\tgpio2: gpio@18180 { /* rework some properties */\n" "> +\t\t\t\tcompatible = \"marvell,orion-gpio\";\n" "> +\t\t\t\treg = <0x18180 0x40>;\n" "> +\t\t\t\tngpios = <1>; /* only gpio #32 */\n" @@ -339,18 +349,18 @@ "> +\t\t\t\tinterrupts = <87>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tnand: nand at d0000 {\n" + "> +\t\t\tnand: nand@d0000 {\n" "> +\t\t\t\tclocks = <&dfx_coredivclk 0>;\n" "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tdfxr: dfx-registers at ac000000 {\n" + "> +\t\tdfxr: dfx-registers@ac000000 {\n" "> +\t\t\tcompatible = \"simple-bus\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;\n" "> +\n" - "> + dfx_coredivclk: corediv-clock at f8268 {\n" + "> + dfx_coredivclk: corediv-clock@f8268 {\n" "> + compatible = \"marvell,mv98dx3236-corediv-clock\";\n" "> + reg = <0xf8268 0xc>;\n" "> + #clock-cells = <1>;\n" @@ -358,19 +368,19 @@ "> + clock-output-names = \"nand\";\n" "> + };\n" "> +\n" - "> +\t\t\tdfx: dfx at 0 {\n" + "> +\t\t\tdfx: dfx@0 {\n" "> +\t\t\t\tcompatible = \"marvell,dfx-server\";\n" "> +\t\t\t\treg = <0 0x100000>;\n" "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tswitch: switch at a8000000 {\n" + "> +\t\tswitch: switch@a8000000 {\n" "> +\t\t\tcompatible = \"simple-bus\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;\n" "> +\n" - "> +\t\t\tpp0: packet-processor at 0 {\n" + "> +\t\t\tpp0: packet-processor@0 {\n" "> +\t\t\t\tcompatible = \"marvell,prestera-98dx3236\";\n" "> +\t\t\t\treg = <0 0x4000000>;\n" "> +\t\t\t\tinterrupts = <33>, <34>, <35>;\n" @@ -461,7 +471,7 @@ "> +\tcompatible = \"marvell,armadaxp-98dx3336\", \"marvell,armadaxp-98dx3236\", \"marvell,armadaxp\", \"marvell,armada-370-xp\";\n" "> +\n" "> +\tcpus {\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"marvell,sheeva-v7\";\n" "> +\t\t\treg = <1>;\n" @@ -472,7 +482,7 @@ "> +\n" "> +\tsoc {\n" "> +\t\tinternal-regs {\n" - "> +\t\t\tresume at 20980 {\n" + "> +\t\t\tresume@20980 {\n" "> +\t\t\t\tcompatible = \"marvell,98dx3336-resume-ctrl\";\n" "> +\t\t\t\treg = <0x20980 0x10>;\n" "> +\t\t\t};\n" @@ -543,7 +553,7 @@ "> +\tcompatible = \"marvell,armadaxp-98dx4521\", \"marvell,armadaxp-98dx3236\", \"marvell,armadaxp\", \"marvell,armada-370-xp\";\n" "> +\n" "> +\tcpus {\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"marvell,sheeva-v7\";\n" "> +\t\t\treg = <1>;\n" @@ -554,7 +564,7 @@ "> +\n" "> +\tsoc {\n" "> +\t\tinternal-regs {\n" - "> +\t\t\tresume at 20980 {\n" + "> +\t\t\tresume@20980 {\n" "> +\t\t\t\tcompatible = \"marvell,98dx3336-resume-ctrl\";\n" "> +\t\t\t\treg = <0x20980 0x10>;\n" "> +\t\t\t};\n" @@ -589,4 +599,4 @@ "development, consulting, training and support.\n" http://free-electrons.com -28b70cbfbabe724c5d877d750d19bca08448b5521c032b8dcc912a2e4f0c66b6 +a92d1a903fed7441e7b37793ed44fb2686b3d6d8794988104fa37bef4528b8ce
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