From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alex =?utf-8?Q?Benn=C3=A9e?= Subject: Re: [kvm-unit-tests PATCH v2 03/10] arm/arm64: smp: support more than 8 cpus Date: Mon, 06 Jun 2016 18:28:57 +0100 Message-ID: <87ziqygrae.fsf@linaro.org> References: <20160606163238.GB23505@leverpostej> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id D7C63412C2 for ; Mon, 6 Jun 2016 13:24:35 -0400 (EDT) Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ygoHfdbluqcc for ; Mon, 6 Jun 2016 13:24:34 -0400 (EDT) Received: from mail-wm0-f49.google.com (mail-wm0-f49.google.com [74.125.82.49]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id C0454410B5 for ; Mon, 6 Jun 2016 13:24:34 -0400 (EDT) Received: by mail-wm0-f49.google.com with SMTP id m124so81612253wme.1 for ; Mon, 06 Jun 2016 10:28:44 -0700 (PDT) In-reply-to: <20160606163238.GB23505@leverpostej> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu To: Mark Rutland Cc: kvm@vger.kernel.org, marc.zyngier@arm.com, andre.przywara@arm.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, pbonzini@redhat.com, kvmarm@lists.cs.columbia.edu List-Id: kvmarm@lists.cs.columbia.edu Ck1hcmsgUnV0bGFuZCA8bWFyay5ydXRsYW5kQGFybS5jb20+IHdyaXRlczoKCj4gT24gTW9uLCBK dW4gMDYsIDIwMTYgYXQgMDU6MjI6NDlQTSArMDEwMCwgQWxleCBCZW5uw6llIHdyb3RlOgo+PiBB bmRyZXcgSm9uZXMgPGRyam9uZXNAcmVkaGF0LmNvbT4gd3JpdGVzOgo+PiA+ICsjZGVmaW5lIE1Q SURSX0xFVkVMX1NISUZUKGxldmVsKSBcCj4+ID4gKwkoKCgxIDw8IGxldmVsKSA+PiAxKSA8PCAz KQo+PiA+ICsjZGVmaW5lIE1QSURSX0FGRklOSVRZX0xFVkVMKG1waWRyLCBsZXZlbCkgXAo+PiA+ ICsJKChtcGlkciA+PiBNUElEUl9MRVZFTF9TSElGVChsZXZlbCkpICYgMHhmZikKPj4KPj4gRG9l c24ndCBBZmYzIGJyZWFrIHRoaXMgbGl0dGxlIG1hY3JvPyBJdCBzaXRzIGF0IDMyOjM5IHdpdGgg YSBnYXAgZm9yCj4+IE1ULCBSRVMwLCBVLCBSRVMxIGZvciBiaXRzIDI1OjMxCj4KPiBJdCB3b3Jr cywgaXQncyBqdXN0IGEgbGl0dGxlIGJpdCBtYWdpYzoKCkFoaCB0aGUgbWFnaWMgd2FzIHRvbyBz dWJ0bGUgZm9yIG15IGV5ZXMsIHBlcmhhcHMgYSBjb21tZW50IGZvciB0aGUKd2FyeS4KCj4KPiAo Z2RiKSBwICgoKDEgPDwgMCkgPj4gMSkgPDwgMykKPiAkMSA9IDAKPiAoZ2RiKSBwICgoKDEgPDwg MSkgPj4gMSkgPDwgMykKPiAkMiA9IDgKPiAoZ2RiKSBwICgoKDEgPDwgMikgPj4gMSkgPDwgMykK PiAkMyA9IDE2Cj4gKGdkYikgcCAoKCgxIDw8IDMpID4+IDEpIDw8IDMpCj4gJDQgPSAzMgo+IChn ZGIpCj4KPiBXZSBkbyB0aGUgc2FtZSBpbiBhcmNoL2FybTY0L2luY2x1ZGUvYXNtL2NwdXR5cGUu aCBzaW5jZSBiMDU4NDUwZjM4YzMzN2QxCj4gKCJhcm02NDoga2VybmVsOiBhZGQgTVBJRFJfRUwx IGFjY2Vzc29ycyBtYWNyb3MiKS4KCkkgc2VlIHRoZSB0cnV0aCBvZiBpdCA7LSkKPgo+IFRoYW5r cywKPiBNYXJrLgoKCi0tCkFsZXggQmVubsOpZQpfX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fXwprdm1hcm0gbWFpbGluZyBsaXN0Cmt2bWFybUBsaXN0cy5jcy5j b2x1bWJpYS5lZHUKaHR0cHM6Ly9saXN0cy5jcy5jb2x1bWJpYS5lZHUvbWFpbG1hbi9saXN0aW5m by9rdm1hcm0K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id hq2sm3114242wjb.36.2016.06.06.10.28.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Jun 2016 10:28:42 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTPS id D6B593E02BF; Mon, 6 Jun 2016 18:28:57 +0100 (BST) User-agent: mu4e 0.9.17; emacs 25.0.94.5 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Mark Rutland Cc: Andrew Jones , kvm@vger.kernel.org, marc.zyngier@arm.com, andre.przywara@arm.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, pbonzini@redhat.com, kvmarm@lists.cs.columbia.edu Subject: Re: [kvm-unit-tests PATCH v2 03/10] arm/arm64: smp: support more than 8 cpus In-reply-to: <20160606163238.GB23505@leverpostej> Date: Mon, 06 Jun 2016 18:28:57 +0100 Message-ID: <87ziqygrae.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-TUID: oKIqTDPqHHz3 Mark Rutland writes: > On Mon, Jun 06, 2016 at 05:22:49PM +0100, Alex Bennée wrote: >> Andrew Jones writes: >> > +#define MPIDR_LEVEL_SHIFT(level) \ >> > + (((1 << level) >> 1) << 3) >> > +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ >> > + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & 0xff) >> >> Doesn't Aff3 break this little macro? It sits at 32:39 with a gap for >> MT, RES0, U, RES1 for bits 25:31 > > It works, it's just a little bit magic: Ahh the magic was too subtle for my eyes, perhaps a comment for the wary. > > (gdb) p (((1 << 0) >> 1) << 3) > $1 = 0 > (gdb) p (((1 << 1) >> 1) << 3) > $2 = 8 > (gdb) p (((1 << 2) >> 1) << 3) > $3 = 16 > (gdb) p (((1 << 3) >> 1) << 3) > $4 = 32 > (gdb) > > We do the same in arch/arm64/include/asm/cputype.h since b058450f38c337d1 > ("arm64: kernel: add MPIDR_EL1 accessors macros"). I see the truth of it ;-) > > Thanks, > Mark. -- Alex Bennée From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35809) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9yKW-0004Ne-5f for qemu-devel@nongnu.org; Mon, 06 Jun 2016 13:28:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b9yKT-0008Lx-0l for qemu-devel@nongnu.org; Mon, 06 Jun 2016 13:28:48 -0400 Received: from mail-wm0-x22b.google.com ([2a00:1450:400c:c09::22b]:38390) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9yKS-0008LJ-7u for qemu-devel@nongnu.org; Mon, 06 Jun 2016 13:28:44 -0400 Received: by mail-wm0-x22b.google.com with SMTP id m124so81612214wme.1 for ; Mon, 06 Jun 2016 10:28:44 -0700 (PDT) From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <20160606163238.GB23505@leverpostej> Date: Mon, 06 Jun 2016 18:28:57 +0100 Message-ID: <87ziqygrae.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [kvm-unit-tests PATCH v2 03/10] arm/arm64: smp: support more than 8 cpus List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Rutland Cc: Andrew Jones , kvm@vger.kernel.org, marc.zyngier@arm.com, andre.przywara@arm.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, pbonzini@redhat.com, kvmarm@lists.cs.columbia.edu Mark Rutland writes: > On Mon, Jun 06, 2016 at 05:22:49PM +0100, Alex Bennée wrote: >> Andrew Jones writes: >> > +#define MPIDR_LEVEL_SHIFT(level) \ >> > + (((1 << level) >> 1) << 3) >> > +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ >> > + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & 0xff) >> >> Doesn't Aff3 break this little macro? It sits at 32:39 with a gap for >> MT, RES0, U, RES1 for bits 25:31 > > It works, it's just a little bit magic: Ahh the magic was too subtle for my eyes, perhaps a comment for the wary. > > (gdb) p (((1 << 0) >> 1) << 3) > $1 = 0 > (gdb) p (((1 << 1) >> 1) << 3) > $2 = 8 > (gdb) p (((1 << 2) >> 1) << 3) > $3 = 16 > (gdb) p (((1 << 3) >> 1) << 3) > $4 = 32 > (gdb) > > We do the same in arch/arm64/include/asm/cputype.h since b058450f38c337d1 > ("arm64: kernel: add MPIDR_EL1 accessors macros"). I see the truth of it ;-) > > Thanks, > Mark. -- Alex Bennée