From mboxrd@z Thu Jan 1 00:00:00 1970 From: Francisco Jerez Subject: Re: [PATCH] drm/i915: Make sure DC writes are coherent on flush. Date: Thu, 14 Jan 2016 09:16:04 -0800 Message-ID: <87ziw8dquj.fsf@riseup.net> References: <1452740379-3194-1-git-send-email-currojerez@riseup.net> <87h9igxxgz.fsf@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1466263129==" Return-path: Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2ED256E00D for ; Thu, 14 Jan 2016 09:16:42 -0800 (PST) In-Reply-To: <87h9igxxgz.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jani Nikula , intel-gfx@lists.freedesktop.org Cc: Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org --===============1466263129== Content-Type: multipart/signed; boundary="==-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" --==-=-= Content-Type: multipart/mixed; boundary="=-=-=" --=-=-= Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Jani Nikula writes: > On Thu, 14 Jan 2016, Francisco Jerez wrote: >> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee >> that writes performed via the HDC are visible in memory. Fixes an >> intermittent failure in a Piglit test that writes to a BO from a >> shader using GL atomic counters (implemented as HDC untyped atomics) >> and then expects the memory to read back the same value after mapping >> it on the CPU. >> >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=3D91298 >> Tested-by: Mark Janes >> Cc: Rodrigo Vivi > > Francisco, this is missing your Signed-off-by i.e. developer certificate > of origin http://developercertificate.org/ - can't push without. Please > reply with that. > Oops, sorry for that -- And yeah it shouldn't hurt to CC stable too. Signed-off-by: Francisco Jerez > BR, > Jani. > > >> --- >> drivers/gpu/drm/i915/intel_lrc.c | 1 + >> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ >> 2 files changed, 3 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/int= el_lrc.c >> index ab344e0..02213c6 100644 >> --- a/drivers/gpu/drm/i915/intel_lrc.c >> +++ b/drivers/gpu/drm/i915/intel_lrc.c >> @@ -1735,6 +1735,7 @@ static int gen8_emit_flush_render(struct drm_i915_= gem_request *request, >> if (flush_domains) { >> flags |=3D PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; >> flags |=3D PIPE_CONTROL_DEPTH_CACHE_FLUSH; >> + flags |=3D PIPE_CONTROL_DC_FLUSH_ENABLE; >> flags |=3D PIPE_CONTROL_FLUSH_ENABLE; >> } >>=20=20 >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i= 915/intel_ringbuffer.c >> index 4060acf..8cd8aab 100644 >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c >> @@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *= req, >> if (flush_domains) { >> flags |=3D PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; >> flags |=3D PIPE_CONTROL_DEPTH_CACHE_FLUSH; >> + flags |=3D PIPE_CONTROL_DC_FLUSH_ENABLE; >> flags |=3D PIPE_CONTROL_FLUSH_ENABLE; >> } >> if (invalidate_domains) { >> @@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *= req, >> if (flush_domains) { >> flags |=3D PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; >> flags |=3D PIPE_CONTROL_DEPTH_CACHE_FLUSH; >> + flags |=3D PIPE_CONTROL_DC_FLUSH_ENABLE; >> flags |=3D PIPE_CONTROL_FLUSH_ENABLE; >> } >> if (invalidate_domains) { > > --=20 > Jani Nikula, Intel Open Source Technology Center --=-=-=-- --==-=-= Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iF4EAREIAAYFAlaX19QACgkQg5k4nX1Sv1vdKAD/SdHEjAQyy65xM7X13PqY4Ewv AvEeqOdN25WG3Doyl+wA/3LJw1N2xazsW4U6e+1fQjLXiOImHpKMRPmOb2CH92Yl =lVf7 -----END PGP SIGNATURE----- --==-=-=-- --===============1466263129== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHA6Ly9saXN0 cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK --===============1466263129==--