From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH] drm/i915: Set the map-and-fenceable flag for preallocated objects Date: Thu, 27 Aug 2015 11:36:01 +0300 Message-ID: <87zj1dw2ku.fsf@intel.com> References: <1440521310-8931-1-git-send-email-chris@chris-wilson.co.uk> <1440590157-4423-1-git-send-email-chris@chris-wilson.co.uk> <20150826130659.GP1367@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 8FFBC6E051 for ; Thu, 27 Aug 2015 01:36:11 -0700 (PDT) In-Reply-To: <20150826130659.GP1367@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter , Chris Wilson Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, "Goel, Akash" , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org T24gV2VkLCAyNiBBdWcgMjAxNSwgRGFuaWVsIFZldHRlciA8ZGFuaWVsQGZmd2xsLmNoPiB3cm90 ZToKPiBPbiBXZWQsIEF1ZyAyNiwgMjAxNSBhdCAxMjo1NTo1N1BNICswMTAwLCBDaHJpcyBXaWxz b24gd3JvdGU6Cj4+IEFzIHdlIG1hcmsgdGhlIHByZWFsbG9jYXRlZCBvYmplY3RzIGFzIGJvdW5k LCB3ZSBzaG91bGQgYWxzbyBmbGFnIHRoZW0KPj4gY29ycmVjdGx5IGFzIGJlaW5nIG1hcC1hbmQt ZmVuY2VhYmxlIChpZiBhcHByb3ByaWF0ZSEpIHNvIHRoYXQgbGF0dGVyCj4+IHVzZXJzIGRvIG5v dCBnZXQgY29uZnVzZWQgYW5kIHRyeSBhbmQgcmViaW5kIHRoZSBwaW5uZWQgdm1hIGluIG9yZGVy IHRvCj4+IGdldCBhIG1hcC1hbmQtZmVuY2VhYmxlIGJpbmRpbmcuCj4+IAo+PiBTaWduZWQtb2Zm LWJ5OiBDaHJpcyBXaWxzb24gPGNocmlzQGNocmlzLXdpbHNvbi5jby51az4KPj4gQ2M6ICJHb2Vs LCBBa2FzaCIgPGFrYXNoLmdvZWxAaW50ZWwuY29tPgo+PiBDYzogRGFuaWVsIFZldHRlciA8ZGFu aWVsLnZldHRlckBmZndsbC5jaD4KPj4gQ2M6IEplc3NlIEJhcm5lcyA8amJhcm5lc0B2aXJ0dW91 c2dlZWsub3JnPgo+PiBDYzogc3RhYmxlQHZnZXIua2VybmVsLm9yZwo+Cj4gUmV2aWV3ZWQtYnk6 IERhbmllbCBWZXR0ZXIgPGRhbmllbC52ZXR0ZXJAZmZ3bGwuY2g+Cj4KPiBKYW5pLCBjYW4geW91 IHBsZWFzZSBwaWNrIHVwIGJvdGg/IEFuZCBzb21lIGJ1Z3ppbGxhIHJlZmVyZW5jZXMgZm9yIGVp dGhlcgo+IHdvdWxkIGJlIGdyZWF0IHRvbyAtIENocmlzPwoKQm90aCBwdXNoZWQgdG8gZHJtLWlu dGVsLW5leHQtZml4ZXMuIFRoYW5rcyBmb3IgdGhlIHBhdGNoZXMgYW5kIHJldmlldy4KCkJSLApK YW5pLgoKPgo+IE9oIGFuZCBkb2VzIHBhdGNoIDEgZml4IHRoZSBleGVjbGlzdCByZXN1bWUgdHJv dWJsZXM/IEV4ZWNsaXN0IGhhdmluZwo+IGJpZ2dlciBjb250ZXh0cyBtaWdodCBiZSBlbm91Z2gg ZXhwbGFuYXRpb25zIGZvciB0aGUgYXBwYXJlbnQgcmVncmVzc2lvbi4KPgo+IEFuZCBjYW4gd2Ug aWd0IHBhdGNoIDEgc29tZWhvdz8gRS5nLiB3aXRoIG1lbW9yeSBwcmVzc3VyZSBwbHVzIGRvaW5n IGFuCj4gbW1hcCBvbiB0aGUgbGVnYWN5IGZiZGV2IC4uLgo+IC1EYW5pZWwKPgo+PiAtLS0KPj4g IGRyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfZHJ2LmggICAgIHwgIDEgKwo+PiAgZHJpdmVycy9n cHUvZHJtL2k5MTUvaTkxNV9nZW0uYyAgICAgfCA0MyArKysrKysrKysrKysrKysrKysrKystLS0t LS0tLS0tLS0tLS0tCj4+ICBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X2dlbV9ndHQuYyB8ICAx ICsKPj4gIDMgZmlsZXMgY2hhbmdlZCwgMjYgaW5zZXJ0aW9ucygrKSwgMTkgZGVsZXRpb25zKC0p Cj4+IAo+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9kcnYuaCBiL2Ry aXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfZHJ2LmgKPj4gaW5kZXggNTU2MTFkODFlYzZjLi5lYzcz MWU2ZGIxMjYgMTAwNjQ0Cj4+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfZHJ2LmgK Pj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9kcnYuaAo+PiBAQCAtMjc5OCw2ICsy Nzk4LDcgQEAgaTkxNV9nZW1fb2JqZWN0X2dndHRfcGluKHN0cnVjdCBkcm1faTkxNV9nZW1fb2Jq ZWN0ICpvYmosCj4+ICAKPj4gIGludCBpOTE1X3ZtYV9iaW5kKHN0cnVjdCBpOTE1X3ZtYSAqdm1h LCBlbnVtIGk5MTVfY2FjaGVfbGV2ZWwgY2FjaGVfbGV2ZWwsCj4+ICAJCSAgdTMyIGZsYWdzKTsK Pj4gK3ZvaWQgX19pOTE1X3ZtYV9zZXRfbWFwX2FuZF9mZW5jZWFibGUoc3RydWN0IGk5MTVfdm1h ICp2bWEpOwo+PiAgaW50IF9fbXVzdF9jaGVjayBpOTE1X3ZtYV91bmJpbmQoc3RydWN0IGk5MTVf dm1hICp2bWEpOwo+PiAgaW50IGk5MTVfZ2VtX29iamVjdF9wdXRfcGFnZXMoc3RydWN0IGRybV9p OTE1X2dlbV9vYmplY3QgKm9iaik7Cj4+ICB2b2lkIGk5MTVfZ2VtX3JlbGVhc2VfYWxsX21tYXBz KHN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdik7Cj4+IGRpZmYgLS1naXQgYS9kcml2 ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X2dlbS5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9n ZW0uYwo+PiBpbmRleCA0MDdiNmIzNTc2YWUuLjM5NTcxZTY3ZjlhNSAxMDA2NDQKPj4gLS0tIGEv ZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9nZW0uYwo+PiArKysgYi9kcml2ZXJzL2dwdS9kcm0v aTkxNS9pOTE1X2dlbS5jCj4+IEBAIC0zOTgwLDYgKzM5ODAsMjkgQEAgaTkxNV92bWFfbWlzcGxh Y2VkKHN0cnVjdCBpOTE1X3ZtYSAqdm1hLCB1aW50MzJfdCBhbGlnbm1lbnQsIHVpbnQ2NF90IGZs YWdzKQo+PiAgCXJldHVybiBmYWxzZTsKPj4gIH0KPj4gIAo+PiArdm9pZCBfX2k5MTVfdm1hX3Nl dF9tYXBfYW5kX2ZlbmNlYWJsZShzdHJ1Y3QgaTkxNV92bWEgKnZtYSkKPj4gK3sKPj4gKwlzdHJ1 Y3QgZHJtX2k5MTVfZ2VtX29iamVjdCAqb2JqID0gdm1hLT5vYmo7Cj4+ICsJYm9vbCBtYXBwYWJs ZSwgZmVuY2VhYmxlOwo+PiArCXUzMiBmZW5jZV9zaXplLCBmZW5jZV9hbGlnbm1lbnQ7Cj4+ICsK Pj4gKwlmZW5jZV9zaXplID0gaTkxNV9nZW1fZ2V0X2d0dF9zaXplKG9iai0+YmFzZS5kZXYsCj4+ ICsJCQkJCSAgIG9iai0+YmFzZS5zaXplLAo+PiArCQkJCQkgICBvYmotPnRpbGluZ19tb2RlKTsK Pj4gKwlmZW5jZV9hbGlnbm1lbnQgPSBpOTE1X2dlbV9nZXRfZ3R0X2FsaWdubWVudChvYmotPmJh c2UuZGV2LAo+PiArCQkJCQkJICAgICBvYmotPmJhc2Uuc2l6ZSwKPj4gKwkJCQkJCSAgICAgb2Jq LT50aWxpbmdfbW9kZSwKPj4gKwkJCQkJCSAgICAgdHJ1ZSk7Cj4+ICsKPj4gKwlmZW5jZWFibGUg PSAodm1hLT5ub2RlLnNpemUgPT0gZmVuY2Vfc2l6ZSAmJgo+PiArCQkgICAgICh2bWEtPm5vZGUu c3RhcnQgJiAoZmVuY2VfYWxpZ25tZW50IC0gMSkpID09IDApOwo+PiArCj4+ICsJbWFwcGFibGUg PSAodm1hLT5ub2RlLnN0YXJ0ICsgZmVuY2Vfc2l6ZSA8PQo+PiArCQkgICAgdG9faTkxNShvYmot PmJhc2UuZGV2KS0+Z3R0Lm1hcHBhYmxlX2VuZCk7Cj4+ICsKPj4gKwlvYmotPm1hcF9hbmRfZmVu Y2VhYmxlID0gbWFwcGFibGUgJiYgZmVuY2VhYmxlOwo+PiArfQo+PiArCj4+ICBzdGF0aWMgaW50 Cj4+ICBpOTE1X2dlbV9vYmplY3RfZG9fcGluKHN0cnVjdCBkcm1faTkxNV9nZW1fb2JqZWN0ICpv YmosCj4+ICAJCSAgICAgICBzdHJ1Y3QgaTkxNV9hZGRyZXNzX3NwYWNlICp2bSwKPj4gQEAgLTQw NDcsMjUgKzQwNzAsNyBAQCBpOTE1X2dlbV9vYmplY3RfZG9fcGluKHN0cnVjdCBkcm1faTkxNV9n ZW1fb2JqZWN0ICpvYmosCj4+ICAKPj4gIAlpZiAoZ2d0dF92aWV3ICYmIGdndHRfdmlldy0+dHlw ZSA9PSBJOTE1X0dHVFRfVklFV19OT1JNQUwgJiYKPj4gIAkgICAgKGJvdW5kIF4gdm1hLT5ib3Vu ZCkgJiBHTE9CQUxfQklORCkgewo+PiAtCQlib29sIG1hcHBhYmxlLCBmZW5jZWFibGU7Cj4+IC0J CXUzMiBmZW5jZV9zaXplLCBmZW5jZV9hbGlnbm1lbnQ7Cj4+IC0KPj4gLQkJZmVuY2Vfc2l6ZSA9 IGk5MTVfZ2VtX2dldF9ndHRfc2l6ZShvYmotPmJhc2UuZGV2LAo+PiAtCQkJCQkJICAgb2JqLT5i YXNlLnNpemUsCj4+IC0JCQkJCQkgICBvYmotPnRpbGluZ19tb2RlKTsKPj4gLQkJZmVuY2VfYWxp Z25tZW50ID0gaTkxNV9nZW1fZ2V0X2d0dF9hbGlnbm1lbnQob2JqLT5iYXNlLmRldiwKPj4gLQkJ CQkJCQkgICAgIG9iai0+YmFzZS5zaXplLAo+PiAtCQkJCQkJCSAgICAgb2JqLT50aWxpbmdfbW9k ZSwKPj4gLQkJCQkJCQkgICAgIHRydWUpOwo+PiAtCj4+IC0JCWZlbmNlYWJsZSA9ICh2bWEtPm5v ZGUuc2l6ZSA9PSBmZW5jZV9zaXplICYmCj4+IC0JCQkgICAgICh2bWEtPm5vZGUuc3RhcnQgJiAo ZmVuY2VfYWxpZ25tZW50IC0gMSkpID09IDApOwo+PiAtCj4+IC0JCW1hcHBhYmxlID0gKHZtYS0+ bm9kZS5zdGFydCArIGZlbmNlX3NpemUgPD0KPj4gLQkJCSAgICBkZXZfcHJpdi0+Z3R0Lm1hcHBh YmxlX2VuZCk7Cj4+IC0KPj4gLQkJb2JqLT5tYXBfYW5kX2ZlbmNlYWJsZSA9IG1hcHBhYmxlICYm IGZlbmNlYWJsZTsKPj4gLQo+PiArCQlfX2k5MTVfdm1hX3NldF9tYXBfYW5kX2ZlbmNlYWJsZSh2 bWEpOwo+PiAgCQlXQVJOX09OKGZsYWdzICYgUElOX01BUFBBQkxFICYmICFvYmotPm1hcF9hbmRf ZmVuY2VhYmxlKTsKPj4gIAl9Cj4+ICAKPj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9p OTE1L2k5MTVfZ2VtX2d0dC5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9nZW1fZ3R0LmMK Pj4gaW5kZXggNGE3NjgwNzE0M2IxLi4xMTJkODRjMzIyNTcgMTAwNjQ0Cj4+IC0tLSBhL2RyaXZl cnMvZ3B1L2RybS9pOTE1L2k5MTVfZ2VtX2d0dC5jCj4+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9p OTE1L2k5MTVfZ2VtX2d0dC5jCj4+IEBAIC0yNTg2LDYgKzI1ODYsNyBAQCBzdGF0aWMgaW50IGk5 MTVfZ2VtX3NldHVwX2dsb2JhbF9ndHQoc3RydWN0IGRybV9kZXZpY2UgKmRldiwKPj4gIAkJCXJl dHVybiByZXQ7Cj4+ICAJCX0KPj4gIAkJdm1hLT5ib3VuZCB8PSBHTE9CQUxfQklORDsKPj4gKwkJ X19pOTE1X3ZtYV9zZXRfbWFwX2FuZF9mZW5jZWFibGUodm1hKTsKPj4gIAl9Cj4+ICAKPj4gIAkv KiBDbGVhciBhbnkgbm9uLXByZWFsbG9jYXRlZCBibG9ja3MgKi8KPj4gLS0gCj4+IDIuNS4wCj4+ IAo+Cj4gLS0gCj4gRGFuaWVsIFZldHRlcgo+IFNvZnR3YXJlIEVuZ2luZWVyLCBJbnRlbCBDb3Jw b3JhdGlvbgo+IGh0dHA6Ly9ibG9nLmZmd2xsLmNoCj4gX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX18KPiBJbnRlbC1nZnggbWFpbGluZyBsaXN0Cj4gSW50ZWwt Z2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwo+IGh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcv bWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngKCi0tIApKYW5pIE5pa3VsYSwgSW50ZWwgT3BlbiBT b3VyY2UgVGVjaG5vbG9neSBDZW50ZXIKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJl ZWRlc2t0b3Aub3JnCmh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5m by9pbnRlbC1nZngK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com ([192.55.52.88]:58341 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751245AbbH0IgL (ORCPT ); Thu, 27 Aug 2015 04:36:11 -0400 From: Jani Nikula To: Daniel Vetter , Chris Wilson Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, stable@vger.kernel.org, "Goel\, Akash" Subject: Re: [Intel-gfx] [PATCH] drm/i915: Set the map-and-fenceable flag for preallocated objects In-Reply-To: <20150826130659.GP1367@phenom.ffwll.local> References: <1440521310-8931-1-git-send-email-chris@chris-wilson.co.uk> <1440590157-4423-1-git-send-email-chris@chris-wilson.co.uk> <20150826130659.GP1367@phenom.ffwll.local> Date: Thu, 27 Aug 2015 11:36:01 +0300 Message-ID: <87zj1dw2ku.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: On Wed, 26 Aug 2015, Daniel Vetter wrote: > On Wed, Aug 26, 2015 at 12:55:57PM +0100, Chris Wilson wrote: >> As we mark the preallocated objects as bound, we should also flag them >> correctly as being map-and-fenceable (if appropriate!) so that latter >> users do not get confused and try and rebind the pinned vma in order to >> get a map-and-fenceable binding. >> >> Signed-off-by: Chris Wilson >> Cc: "Goel, Akash" >> Cc: Daniel Vetter >> Cc: Jesse Barnes >> Cc: stable@vger.kernel.org > > Reviewed-by: Daniel Vetter > > Jani, can you please pick up both? And some bugzilla references for either > would be great too - Chris? Both pushed to drm-intel-next-fixes. Thanks for the patches and review. BR, Jani. > > Oh and does patch 1 fix the execlist resume troubles? Execlist having > bigger contexts might be enough explanations for the apparent regression. > > And can we igt patch 1 somehow? E.g. with memory pressure plus doing an > mmap on the legacy fbdev ... > -Daniel > >> --- >> drivers/gpu/drm/i915/i915_drv.h | 1 + >> drivers/gpu/drm/i915/i915_gem.c | 43 +++++++++++++++++++++---------------- >> drivers/gpu/drm/i915/i915_gem_gtt.c | 1 + >> 3 files changed, 26 insertions(+), 19 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> index 55611d81ec6c..ec731e6db126 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -2798,6 +2798,7 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, >> >> int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, >> u32 flags); >> +void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); >> int __must_check i915_vma_unbind(struct i915_vma *vma); >> int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); >> void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); >> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c >> index 407b6b3576ae..39571e67f9a5 100644 >> --- a/drivers/gpu/drm/i915/i915_gem.c >> +++ b/drivers/gpu/drm/i915/i915_gem.c >> @@ -3980,6 +3980,29 @@ i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) >> return false; >> } >> >> +void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) >> +{ >> + struct drm_i915_gem_object *obj = vma->obj; >> + bool mappable, fenceable; >> + u32 fence_size, fence_alignment; >> + >> + fence_size = i915_gem_get_gtt_size(obj->base.dev, >> + obj->base.size, >> + obj->tiling_mode); >> + fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, >> + obj->base.size, >> + obj->tiling_mode, >> + true); >> + >> + fenceable = (vma->node.size == fence_size && >> + (vma->node.start & (fence_alignment - 1)) == 0); >> + >> + mappable = (vma->node.start + fence_size <= >> + to_i915(obj->base.dev)->gtt.mappable_end); >> + >> + obj->map_and_fenceable = mappable && fenceable; >> +} >> + >> static int >> i915_gem_object_do_pin(struct drm_i915_gem_object *obj, >> struct i915_address_space *vm, >> @@ -4047,25 +4070,7 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj, >> >> if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && >> (bound ^ vma->bound) & GLOBAL_BIND) { >> - bool mappable, fenceable; >> - u32 fence_size, fence_alignment; >> - >> - fence_size = i915_gem_get_gtt_size(obj->base.dev, >> - obj->base.size, >> - obj->tiling_mode); >> - fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, >> - obj->base.size, >> - obj->tiling_mode, >> - true); >> - >> - fenceable = (vma->node.size == fence_size && >> - (vma->node.start & (fence_alignment - 1)) == 0); >> - >> - mappable = (vma->node.start + fence_size <= >> - dev_priv->gtt.mappable_end); >> - >> - obj->map_and_fenceable = mappable && fenceable; >> - >> + __i915_vma_set_map_and_fenceable(vma); >> WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); >> } >> >> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c >> index 4a76807143b1..112d84c32257 100644 >> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c >> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c >> @@ -2586,6 +2586,7 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev, >> return ret; >> } >> vma->bound |= GLOBAL_BIND; >> + __i915_vma_set_map_and_fenceable(vma); >> } >> >> /* Clear any non-preallocated blocks */ >> -- >> 2.5.0 >> > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center