From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38680) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZLClo-0008OJ-Fb for qemu-devel@nongnu.org; Fri, 31 Jul 2015 12:02:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZLCll-0002Bg-9N for qemu-devel@nongnu.org; Fri, 31 Jul 2015 12:02:52 -0400 Received: from mail-wi0-f178.google.com ([209.85.212.178]:38275) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZLCll-0002BU-4j for qemu-devel@nongnu.org; Fri, 31 Jul 2015 12:02:49 -0400 Received: by wibxm9 with SMTP id xm9so37986600wib.1 for ; Fri, 31 Jul 2015 09:02:48 -0700 (PDT) References: <1437755447-10537-1-git-send-email-aurelien@aurel32.net> <1437755447-10537-11-git-send-email-aurelien@aurel32.net> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1437755447-10537-11-git-send-email-aurelien@aurel32.net> Date: Fri, 31 Jul 2015 17:02:46 +0100 Message-ID: <87zj2cfh7d.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH for-2.5 10/10] tcg: update README about size changing ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: qemu-devel@nongnu.org, Richard Henderson Aurelien Jarno writes: > Cc: Richard Henderson > Signed-off-by: Aurelien Jarno > --- > tcg/README | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) > > diff --git a/tcg/README b/tcg/README > index 61b3899..a22f251 100644 > --- a/tcg/README > +++ b/tcg/README > @@ -466,13 +466,25 @@ On a 32 bit target, all 64 bit operations are converted to 32 bits. A > few specific operations must be implemented to allow it (see add2_i32, > sub2_i32, brcond2_i32). > > +On a 64 bit target, the values are transfered between 32 and 64-bit > +registers using the following ops: > +- trunc_shr_i64_i32 > +- ext_i32_i64 > +- extu_i32_i64 > + > +They ensure that the values are correctly truncated or extended when > +moved from a 32-bit to a 64-bit register or vice-versa. Note that the > +trunc_shr_i64_i32 is an optional op. It is not necessary to implement > +it if all the following conditions are met: > +- 64-bit registers can hold 32-bit values > +- 32-bit values in a 64-bit register do not need to stay zero or > + sign extended > +- all 32-bit TCG ops ignore the high part of 64-bit registers > + > Floating point operations are not supported in this version. A > previous incarnation of the code generator had full support of them, > but it is better to concentrate on integer operations first. > > -On a 64 bit target, no assumption is made in TCG about the storage of > -the 32 bit values in 64 bit registers. > - > 4.2) Constraints > > GCC like constraints are used to define the constraints of every I would include patches to the README with the respective patches that introduced the changes. It is basically an extended comment ;-) -- Alex Bennée