From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35273) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCvW7-0000cW-AR for qemu-devel@nongnu.org; Tue, 05 Mar 2013 12:19:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCvW6-0004UJ-1W for qemu-devel@nongnu.org; Tue, 05 Mar 2013 12:19:07 -0500 Received: from e23smtp03.au.ibm.com ([202.81.31.145]:49076) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCvW5-0004U5-GL for qemu-devel@nongnu.org; Tue, 05 Mar 2013 12:19:05 -0500 Received: from /spool/local by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 6 Mar 2013 03:12:37 +1000 Received: from d23relay05.au.ibm.com (d23relay05.au.ibm.com [9.190.235.152]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id 6446B3578050 for ; Wed, 6 Mar 2013 04:18:55 +1100 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay05.au.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r25H6Amc62324788 for ; Wed, 6 Mar 2013 04:06:10 +1100 Received: from d23av03.au.ibm.com (loopback [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r25HIsxS019493 for ; Wed, 6 Mar 2013 04:18:54 +1100 From: Anthony Liguori In-Reply-To: <1362495898-15352-4-git-send-email-pbonzini@redhat.com> References: <1362495898-15352-1-git-send-email-pbonzini@redhat.com> <1362495898-15352-4-git-send-email-pbonzini@redhat.com> Date: Tue, 05 Mar 2013 11:18:46 -0600 Message-ID: <87zjyhrci1.fsf@codemonkey.ws> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Subject: Re: [Qemu-devel] [PATCH 3/3] hw: correctly implement soft reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Cc: dwmw2@infradead.org, lersek@redhat.com Paolo Bonzini writes: > Do not do a hard reset for port 92h, keyboard controller, or cf9h soft reset. > These only reset the CPU. > > Signed-off-by: Paolo Bonzini I'm quite confident these devices should trigger a soft reset but not confident this is exhaustive. Reviewed-by: Anthony Liguori Regards, Anthony Liguori > --- > hw/lpc_ich9.c | 7 ++++++- > hw/pc.c | 3 ++- > hw/pckbd.c | 5 +++-- > hw/piix_pci.c | 8 ++++++-- > 4 files changed, 17 insertions(+), 6 deletions(-) > > diff --git a/hw/lpc_ich9.c b/hw/lpc_ich9.c > index eceb052..fae31df 100644 > --- a/hw/lpc_ich9.c > +++ b/hw/lpc_ich9.c > @@ -45,6 +45,7 @@ > #include "pci/pci_bus.h" > #include "exec/address-spaces.h" > #include "sysemu/sysemu.h" > +#include "sysemu/cpus.h" > > static int ich9_lpc_sci_irq(ICH9LPCState *lpc); > > @@ -506,7 +507,11 @@ static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, > ICH9LPCState *lpc = opaque; > > if (val & 4) { > - qemu_system_reset_request(); > + if (val & 0xA) { > + qemu_system_reset_request(); > + } else { > + cpu_soft_reset(); > + } > return; > } > lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ > diff --git a/hw/pc.c b/hw/pc.c > index 523db1f..6080d62 100644 > --- a/hw/pc.c > +++ b/hw/pc.c > @@ -45,6 +45,7 @@ > #include "kvm_i386.h" > #include "xen.h" > #include "sysemu/blockdev.h" > +#include "sysemu/cpus.h" > #include "hw/block-common.h" > #include "ui/qemu-spice.h" > #include "exec/memory.h" > @@ -441,7 +442,7 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val, > s->outport = val; > qemu_set_irq(*s->a20_out, (val >> 1) & 1); > if ((val & 1) && !(oldval & 1)) { > - qemu_system_reset_request(); > + cpu_soft_reset(); > } > } > > diff --git a/hw/pckbd.c b/hw/pckbd.c > index 3bad09b..fd66788 100644 > --- a/hw/pckbd.c > +++ b/hw/pckbd.c > @@ -26,6 +26,7 @@ > #include "pc.h" > #include "ps2.h" > #include "sysemu/sysemu.h" > +#include "sysemu/cpus.h" > > /* debug PC keyboard */ > //#define DEBUG_KBD > @@ -220,7 +221,7 @@ static void outport_write(KBDState *s, uint32_t val) > qemu_set_irq(*s->a20_out, (val >> 1) & 1); > } > if (!(val & 1)) { > - qemu_system_reset_request(); > + cpu_soft_reset(); > } > } > > @@ -299,7 +300,7 @@ static void kbd_write_command(void *opaque, hwaddr addr, > s->outport &= ~KBD_OUT_A20; > break; > case KBD_CCMD_RESET: > - qemu_system_reset_request(); > + cpu_soft_reset(); > break; > case KBD_CCMD_NO_OP: > /* ignore that */ > diff --git a/hw/piix_pci.c b/hw/piix_pci.c > index 6c77e49..785e0a7 100644 > --- a/hw/piix_pci.c > +++ b/hw/piix_pci.c > @@ -32,6 +32,7 @@ > #include "xen.h" > #include "pam.h" > #include "sysemu/sysemu.h" > +#include "sysemu/cpus.h" > > /* > * I440FX chipset data sheet. > @@ -521,8 +522,11 @@ static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) > PIIX3State *d = opaque; > > if (val & 4) { > - qemu_system_reset_request(); > - return; > + if (val & 2) { > + qemu_system_reset_request(); > + } else { > + cpu_soft_reset(); > + } > } > d->rcr = val & 2; /* keep System Reset type only */ > } > -- > 1.8.1.4