From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:56560) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCtwy-0007Iy-Mr for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:38:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCtww-0001QA-S3 for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:38:44 -0500 Received: from e23smtp06.au.ibm.com ([202.81.31.148]:50836) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCtww-0001Pk-1q for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:38:42 -0500 Received: from /spool/local by e23smtp06.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 6 Mar 2013 01:33:46 +1000 Received: from d23relay04.au.ibm.com (d23relay04.au.ibm.com [9.190.234.120]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id E25A43578053 for ; Wed, 6 Mar 2013 02:38:35 +1100 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay04.au.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r25FPxSW65274106 for ; Wed, 6 Mar 2013 02:26:00 +1100 Received: from d23av03.au.ibm.com (loopback [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r25FcYDr026440 for ; Wed, 6 Mar 2013 02:38:34 +1100 From: Anthony Liguori In-Reply-To: <1362495898-15352-2-git-send-email-pbonzini@redhat.com> References: <1362495898-15352-1-git-send-email-pbonzini@redhat.com> <1362495898-15352-2-git-send-email-pbonzini@redhat.com> Date: Tue, 05 Mar 2013 09:38:20 -0600 Message-ID: <87zjyhsvpv.fsf@codemonkey.ws> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Subject: Re: [Qemu-devel] [PATCH 1/3] cpu: make CPU_INTERRUPT_RESET available on all targets List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Cc: lersek@redhat.com, dwmw2@infradead.org Paolo Bonzini writes: > On the x86, some devices need access to the CPU reset pin (INIT#). > Provide a generic service to do this, using one of the internal > cpu_interrupt targets. Generalize the PPC-specific code for > CPU_INTERRUPT_RESET to other targets, and provide a function that > will raise the interrupt on all CPUs. > > Since PPC does not support migration, I picked the value that is > used on x86, CPU_INTERRUPT_TGT_INT_1. No other arch used to use > CPU_INTERRUPT_TGT_INT_1. > > Signed-off-by: Paolo Bonzini This is a very nice approach. It would still be nice to remove the explicit reset registrations for the various cpus and instead just call cpu_soft_reset(). I'm not sure "soft" is the best word. This is just a normal CPU reset but I won't bikeshed over that. Reviewed-by: Anthony Liguori Regards, Anthony Liguori > --- > cpu-exec.c | 24 ++++++++++++++---------- > cpus.c | 9 +++++++++ > include/exec/cpu-all.h | 8 +++++--- > include/sysemu/cpus.h | 1 + > target-i386/cpu.h | 7 ++++--- > 5 files changed, 33 insertions(+), 16 deletions(-) > > diff --git a/cpu-exec.c b/cpu-exec.c > index 9092145..e48bb6c 100644 > --- a/cpu-exec.c > +++ b/cpu-exec.c > @@ -300,19 +300,26 @@ int cpu_exec(CPUArchState *env) > } > #endif > #if defined(TARGET_I386) > -#if !defined(CONFIG_USER_ONLY) > - if (interrupt_request & CPU_INTERRUPT_POLL) { > - env->interrupt_request &= ~CPU_INTERRUPT_POLL; > - apic_poll_irq(env->apic_state); > - } > -#endif > if (interrupt_request & CPU_INTERRUPT_INIT) { > cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, > 0); > do_cpu_init(x86_env_get_cpu(env)); > env->exception_index = EXCP_HALTED; > cpu_loop_exit(env); > - } else if (interrupt_request & CPU_INTERRUPT_SIPI) { > + } > +#else > + if ((interrupt_request & CPU_INTERRUPT_RESET)) { > + cpu_reset(cpu); > + } > +#endif > +#if defined(TARGET_I386) > +#if !defined(CONFIG_USER_ONLY) > + if (interrupt_request & CPU_INTERRUPT_POLL) { > + env->interrupt_request &= ~CPU_INTERRUPT_POLL; > + apic_poll_irq(env->apic_state); > + } > +#endif > + if (interrupt_request & CPU_INTERRUPT_SIPI) { > do_cpu_sipi(x86_env_get_cpu(env)); > } else if (env->hflags2 & HF2_GIF_MASK) { > if ((interrupt_request & CPU_INTERRUPT_SMI) && > @@ -365,9 +372,6 @@ int cpu_exec(CPUArchState *env) > } > } > #elif defined(TARGET_PPC) > - if ((interrupt_request & CPU_INTERRUPT_RESET)) { > - cpu_reset(cpu); > - } > if (interrupt_request & CPU_INTERRUPT_HARD) { > ppc_hw_interrupt(env); > if (env->pending_interrupts == 0) > diff --git a/cpus.c b/cpus.c > index c4b021d..665175d 100644 > --- a/cpus.c > +++ b/cpus.c > @@ -405,6 +405,15 @@ void hw_error(const char *fmt, ...) > abort(); > } > > +void cpu_soft_reset(void) > +{ > + CPUArchState *env; > + > + for (env = first_cpu; env; env = env->next_cpu) { > + cpu_interrupt(env, CPU_INTERRUPT_RESET); > + } > +} > + > void cpu_synchronize_all_states(void) > { > CPUArchState *cpu; > diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h > index 249e046..1361d22 100644 > --- a/include/exec/cpu-all.h > +++ b/include/exec/cpu-all.h > @@ -392,6 +392,9 @@ DECLARE_TLS(CPUArchState *,cpu_single_env); > /* Debug event pending. */ > #define CPU_INTERRUPT_DEBUG 0x0080 > > +/* Reset signal. */ > +#define CPU_INTERRUPT_RESET 0x0400 > + > /* Several target-specific external hardware interrupts. Each target/cpu.h > should define proper names based on these defines. */ > #define CPU_INTERRUPT_TGT_EXT_0 0x0008 > @@ -406,9 +409,8 @@ DECLARE_TLS(CPUArchState *,cpu_single_env); > instruction being executed. These, therefore, are not masked while > single-stepping within the debugger. */ > #define CPU_INTERRUPT_TGT_INT_0 0x0100 > -#define CPU_INTERRUPT_TGT_INT_1 0x0400 > -#define CPU_INTERRUPT_TGT_INT_2 0x0800 > -#define CPU_INTERRUPT_TGT_INT_3 0x2000 > +#define CPU_INTERRUPT_TGT_INT_1 0x0800 > +#define CPU_INTERRUPT_TGT_INT_2 0x2000 > > /* First unused bit: 0x4000. */ > > diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h > index 6502488..87b9829 100644 > --- a/include/sysemu/cpus.h > +++ b/include/sysemu/cpus.h > @@ -7,6 +7,7 @@ void resume_all_vcpus(void); > void pause_all_vcpus(void); > void cpu_stop_current(void); > > +void cpu_soft_reset(void); > void cpu_synchronize_all_states(void); > void cpu_synchronize_all_post_reset(void); > void cpu_synchronize_all_post_init(void); > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index 493dda8..73dacdd 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -577,10 +577,11 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 > #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 > #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 > -#define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1 > -#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2 > -#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_3 > +#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 > +#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 > > +/* CPU_INTERRUPT_RESET acts as the INIT# pin. */ > +#define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET > > typedef enum { > CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ > -- > 1.8.1.4