From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 03/22] drm/i915: add UCGCTL4 to display reg check on VLV Date: Wed, 06 Feb 2013 14:53:57 +0200 Message-ID: <87zjzhob6i.fsf@intel.com> References: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> <1359809786-26434-4-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 5B7F6E5CB8 for ; Wed, 6 Feb 2013 04:54:34 -0800 (PST) In-Reply-To: <1359809786-26434-4-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sat, 02 Feb 2013, Jesse Barnes wrote: > Add a few regs needed for various clock gating init purposes and make > sure they don't fall into the display offset range on VLV. GEN7_UCGCTL4 needs to be fixed in i915_reg.h after IS_DISPLAYREG removal. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_drv.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 69d0637..13b9b4f 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1208,6 +1208,7 @@ static bool IS_DISPLAYREG(u32 reg) > case GEN7_HALF_SLICE_CHICKEN1: > case GEN6_MBCTL: > case GEN6_UCGCTL2: > + case GEN7_UCGCTL4: > return false; > default: > break; > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx