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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [RFC PATCH v3] doc: arch: Add document for RISC-V architecture Content-Language: en-US To: Yu Chien Peter Lin Cc: ycliang@andestech.com, rick@andestech.com, sjg@chromium.org, Samuel Holland , u-boot@lists.denx.de References: <20230214101851.11648-1-peterlin@andestech.com> From: Heinrich Schuchardt In-Reply-To: <20230214101851.11648-1-peterlin@andestech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:JRKiHXlhqifyp2umCKUdtlhjcuAB/dKYmeybTzd5i0TStsDQyAU 9ZCNBq0BmJFpyl/rz+z/yfTyHSCRDFitjsaQmNZkj+jNfEKZ9znR8VkNSQxV4BMPXlxHmbQ 00lmfRk+9zChBiimKP/a9zLbWid7rXFD0HBzqRElAGVzVjpRy33x8o6wFi17DFUKj/FGHoy h/1EcnYpPFLflXJilRtAg== UI-OutboundReport: notjunk:1;M01:P0:sMJsImRQtvw=;MgfPxoond3dj7sedo8hPfqfP6SK wW6vrYTa+qKIlEfvnBZQWVRNghHtukq8W76G6nQyICkxxHN/RZ0jPfVtWHp6u1TS4bOzhBNLl bWRElLuKP9SUVSg5QBB7xiv/r2VXwV4yyk7tBuzYJZfDl8mXybguZlwN39wy1lu3wY+fEAsXM 5E79216jqhQheWndTmrSnmTUdT9yV5b/85P2IPq8CEfPTJlaQZnLn/cp6qQ5yJ1TpaVYGMsn2 0BoU8/rdscEioW2ww/aKNQpyTpvHY60g7b+pp7lF2wyiv7e+JTyAJJzFDvutrM+rwyuJAHWKJ 7LgFg81F0rerkO1di/3VAxIUxNvyZp0WvRxIin7+eaZeoBgB/92GBz2HhhOeU9+1uP3HQePIi c/IO4XMFKz8hqvbCsBXoUMT8aB/soX0VQNU1uf2XqMvqlosdh3nNqk2O3gN8/HLS7Cb6Qzspo vw0cxLY77zJhfZnStpNqbFmugeKB5xmJhid4I5NZqwC72IX1WNVpXWbcJT92UQzInAKiftvMp xy9C0cOIdQXvM4l0aXEjMVY1Kkocgj1ctrH5XeDYUvWgQkN3Of1xGGSMw2CrcumeZtjj9JKd7 2FjtvcyYKd1S64XyBLyyvlut/APYm881FZO+T+bjVU8jCsd2PMFfF/bGnFgts8buE1bbD6h4V az0rg/iKizxeF1n0cYuTQXAxDB4brr/QAhVHfQKbx0b/8uooR7fPrLNdvTV85EwK6em0cYvlE V5EPMgMsxEsufJazsIF52UfwS0V5fDb4La7eMRaRClGyHNx6lnfnw3iN52uljNwPEF4tbZtO4 msQ71vGdGiE02AKpj3xDu2pEcqpJCd4/5HCvnbwXKKLudbHtlA6oyY1EhXI4ujAojrs/yV7Zq SPttrN1UKv4QM1hU/Zog1E/T3P/C72FoC4LAhoozyVbH5WgQK+kDUeP/g7mDk0nW0g2n4htk7 6nKRCWDYi4BEcufWd4Y01d/XhrE= X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On 2/14/23 11:18, Yu Chien Peter Lin wrote: > This patch adds a brief introduction to the RISC-V architecture and > the typical boot process used on a variety of RISC-V platforms. > > Signed-off-by: Yu Chien Peter Lin > Reviewed-by: Samuel Holland > Reviewed-by: Simon Glass > Reviewed-by: Rick Chen > --- > Changes v1 -> v2 > - Use 'boot phases' rather than 'boot stages' > - Pick up Samuel and Simon's RB tags > Changes v2 -> v3 > - Follow the suggestion by Heinrich [1] > - Add the document as an entry of Andes maintainer in MAINTAINERS > - Add some pointers to OpenSBI document > > [1] https://patchwork.ozlabs.org/project/uboot/patch/20230212070053.1480= 0-1-peterlin@andestech.com/ > --- > MAINTAINERS | 1 + > doc/arch/index.rst | 1 + > doc/arch/riscv.rst | 74 ++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 76 insertions(+) > create mode 100644 doc/arch/riscv.rst > > diff --git a/MAINTAINERS b/MAINTAINERS > index b9c505d5fa..5eb79faf29 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1292,6 +1292,7 @@ S: Maintained > T: git https://source.denx.de/u-boot/custodians/u-boot-riscv.git > F: arch/riscv/ > F: cmd/riscv/ > +F: doc/arch/riscv.rst > F: doc/usage/sbi.rst > F: drivers/sysreset/sysreset_sbi.c > F: drivers/timer/andes_plmt_timer.c > diff --git a/doc/arch/index.rst b/doc/arch/index.rst > index b3e85f9bf3..b8da4b8c8e 100644 > --- a/doc/arch/index.rst > +++ b/doc/arch/index.rst > @@ -11,6 +11,7 @@ Architecture-specific doc > m68k > mips > nios2 > + riscv > sandbox/index > sh > x86 > diff --git a/doc/arch/riscv.rst b/doc/arch/riscv.rst > new file mode 100644 > index 0000000000..10bf3e6849 > --- /dev/null > +++ b/doc/arch/riscv.rst > @@ -0,0 +1,74 @@ > +.. SPDX-License-Identifier: GPL-2.0+ > +.. Copyright (C) 2023, Yu Chien Peter Lin > + > +RISC-V > +=3D=3D=3D=3D=3D=3D > + > +Overview > +-------- > + > +This document outlines the U-Boot boot process for the RISC-V architect= ure. > +RISC-V is an open-source instruction set architecture (ISA) based on th= e > +principles of reduced instruction set computing (RISC). It has been des= igned > +to be flexible and customizable, allowing it to be adapted to different= use > +cases, from embedded systems to high performance servers. > + > +Typical Boot Process > +-------------------- > + > +U-Boot can run in either M-mode or S-mode, depending on whether it runs= before > +the initialization of the firmware providing SBI (Supervisor Binary Int= erface). > +The firmware is necessary in the RISC-V boot process as it serves as a = SEE > +(Supervisor Execution Environment) to handle exceptions for the S-mode = U-Boot > +or Operating System. > + > +In between the boot phases, the hartid is passed through the a0 registe= r, and > +the start address of the devicetree is passed through the a1 register. > + > +As a reference, OpenSBI is an SBI implementation that can be used with = U-Boot > +in different modes, see the `OpenSBI firmware document `_ for more detai= ls. > + > +M-mode U-Boot > +^^^^^^^^^^^^^ > + > +When running in M-mode U-Boot, it will load the payload image (e.g. `fw= _payload `_) > +which contains the firmware and the S-mode Operating System; in this ca= se, you > +can use mkimage to package the payload image into an uImage format, and= boot it > +using the bootm command. > + > +The following diagram illustrates the boot process:: > + > + <-----------( M-mode )----------><--( S-mode )--> > + +----------+ +--------------+ +------------+ > + | U-Boot |-->| SBI firmware |--->| OS | > + +----------+ +--------------+ +------------+ > + > +To examine the boot process with the QEMU virt machine, you can follow = the > +steps in the "Building U-Boot" section of the following document: > +:doc:`../board/emulation/qemu-riscv.rst` This patch does not build. '.rst' has to removed here. doc/arch/riscv.rst:46:unknown document: ../board/emulation/qemu-riscv.rst make[1]: *** [doc/Makefile:70: htmldocs] Error 2 make: *** [Makefile:2348: htmldocs] Error 2 Please, execute the build process as described in https://u-boot.readthedocs.io/en/latest/build/documentation.html#html-docu= mentation for testing your documentation patches. I will fix this issue when merging. Thank you for the contribution. Best regards Heinrich > + > +S-mode U-Boot > +^^^^^^^^^^^^^ > + > +RISC-V production boot images may include a U-Boot SPL for platform-spe= cific > +initialization. The U-Boot SPL then loads a FIT image (u-boot.itb), whi= ch > +contains a firmware (e.g. `fw_dynamic `_) providing the SB= I, as well as a regular > +U-Boot (or U-Boot proper) running in S-mode. Finally, the S-mode Operat= ing > +System is loaded. > + > +The following diagram illustrates the boot process:: > + > + <-------------( M-mode )----------><----------( S-mode )-------> > + +------------+ +--------------+ +----------+ +----------+ > + | U-Boot SPL |-->| SBI firmware |--->| U-Boot |-->| OS | > + +------------+ +--------------+ +----------+ +----------+ > + > +To examine the boot process with the QEMU virt machine, you can follow = the > +steps in the "Running U-Boot SPL" section of the following document: > +:doc:`../board/emulation/qemu-riscv.rst` > + > +Toolchain > +--------- > + > +You can build the `RISC-V GNU toolchain `_ from scratch, or download a > +pre-built toolchain from the `releases page `_.