From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Ryan Brue <ryanbrue.dev@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Chen-Yu Tsai <wenst@chromium.org>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: Re: [PATCH 2/2] clk: mediatek: mt6795: fix the FHCTL DDS mask width
Date: Mon, 14 Sep 2026 10:16:10 +0200 [thread overview]
Message-ID: <88272aca-2a9e-4a75-b7f2-4f7aac8b6d18@collabora.com> (raw)
In-Reply-To: <20260912-mt8173-fix-dds-mask-width-v1-2-3d0c0292c85c@gmail.com>
On 9/12/26 08:40, Ryan Brue wrote:
> All eight PLLs in mt6795's pllfhs[] have pcwbits = 21, so the FHCTL DDS
> field is bits 20:0, but _FH() declares .dds_mask = GENMASK(21, 0). As on
> MT8173, new_dds from mtk_pll_calc_values() is always 21-bit, so admitting
> bit 21 of FHCTL_MON into the poll in hopping_hw_flow() can only make it
> time out. The same mask feeds the CON1 write-back and fhctl_set_ssc_regs().
>
> Unlike MT8173 this path has a user: mt6795-sony-xperia-m5.dts switches
> FHCTL on for mainpll, mpll and msdcpll, with SSC.
>
> Found by inspection while fixing MT8173. I have no MT6795 hardware, so
> this one is untested.
>
> Fixes: f222a1baec5f ("clk: mediatek: mt6795: Add support for frequency hopping through FHCTL")
> Assisted-by: LLM
> Signed-off-by: Ryan Brue <ryanbrue.dev@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
next prev parent reply other threads:[~2026-09-14 8:16 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-12 6:40 [PATCH 0/2] clk: mediatek: Fix FHCTL DDS mask widths for mt8173, mt6795 Ryan Brue
2026-09-12 6:40 ` [PATCH 1/2] clk: mediatek: mt8173: fix the FHCTL DDS mask width Ryan Brue
2026-09-12 6:50 ` sashiko-bot
2026-09-14 8:16 ` AngeloGioacchino Del Regno
2026-09-12 6:40 ` [PATCH 2/2] clk: mediatek: mt6795: " Ryan Brue
2026-09-14 8:16 ` AngeloGioacchino Del Regno [this message]
2026-09-25 13:13 ` Jerome Brunet
2026-09-28 12:22 ` AngeloGioacchino Del Regno
2026-10-17 23:03 ` Ryan Brue
2026-10-21 13:21 ` Jerome Brunet
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