[U-Boot] [PATCH 1/2] mx5: Add default pin initializers

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From: "Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/2] mx5: Add default pin initializers
Date: Tue, 14 Aug 2012 17:46:54 +0200 (CEST)	[thread overview]
Message-ID: <883852451.2404814.1344959214390.JavaMail.root@advansee.com> (raw)

Create default pin initialization functions for the default iomux function
assignments of the main peripherals.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 .../arch/arm/cpu/armv7/mx5/soc.c                   |  139 ++++++++++++++++++++
 .../arch/arm/include/asm/arch-mx5/sys_proto.h      |    5 +
 2 files changed, 144 insertions(+)

diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c
index 3f5a4f7..ee19b54 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c
@@ -25,6 +25,8 @@
 
 #include <common.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 
@@ -71,6 +73,143 @@ u32 get_cpu_rev(void)
 	return system_rev;
 }
 
+#ifdef CONFIG_MXC_UART
+#if CONFIG_MXC_UART_BASE == UART1_BASE
+#ifdef CONFIG_MX51
+void mx51_uart1_init_pins(void)
+{
+	int in_pad, out_pad;
+
+	/* Set up pins for UART1. */
+	mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
+
+	mxc_iomux_set_input(MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+			    INPUT_CTL_PATH0);
+	mxc_iomux_set_input(MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+			    INPUT_CTL_PATH0);
+
+	in_pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+		PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW;
+	out_pad = PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE |
+		PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_SRE_SLOW;
+
+	mxc_iomux_set_pad(MX51_PIN_UART1_RXD, in_pad);
+	mxc_iomux_set_pad(MX51_PIN_UART1_TXD, out_pad);
+	mxc_iomux_set_pad(MX51_PIN_UART1_RTS, in_pad);
+	mxc_iomux_set_pad(MX51_PIN_UART1_CTS, out_pad);
+}
+#endif
+#endif
+#endif
+
+#ifdef CONFIG_MXC_SPI
+void mx51_ecspi1_init_pins(void)
+{
+	int act_lo_pad, act_hi_pad;
+
+	/* Set up pins for eCSPI1. */
+	mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT0);
+
+	act_lo_pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_PULL | PAD_CTL_100K_PU |
+		PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_SRE_SLOW;
+	act_hi_pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_PULL | PAD_CTL_100K_PD |
+		PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_SRE_SLOW;
+
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, act_hi_pad);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, act_lo_pad);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, act_hi_pad);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, act_hi_pad);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, act_lo_pad);
+	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, act_lo_pad);
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+void mx51_esdhc1_init_pins(void)
+{
+	int out_pad, io_pad;
+
+	/* Set up pins for eSDHC1. */
+	mxc_request_iomux(MX51_PIN_SD1_CMD,
+			  IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_SD1_DATA0,
+			  IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_SD1_DATA1,
+			  IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_SD1_DATA2,
+			  IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_SD1_DATA3,
+			  IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_GPIO1_1,
+			  IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); /* WP */
+	mxc_request_iomux(MX51_PIN_GPIO1_0,
+			  IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); /* CD */
+
+	out_pad = PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_PULL | PAD_CTL_47K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST;
+	io_pad = PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_47K_PU |
+		PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST;
+
+	mxc_iomux_set_pad(MX51_PIN_SD1_CMD, io_pad);
+	mxc_iomux_set_pad(MX51_PIN_SD1_CLK, out_pad);
+	mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, io_pad);
+	mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, io_pad);
+	mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, io_pad);
+	mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, io_pad);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_1, PAD_CTL_HYS_ENABLE); /* WP */
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_0, PAD_CTL_HYS_ENABLE); /* CD */
+}
+
+void mx51_esdhc2_init_pins(void)
+{
+	int out_pad, io_pad;
+
+	/* Set up pins for eSDHC2. */
+	mxc_request_iomux(MX51_PIN_SD2_CMD,
+			  IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_SD2_DATA0,
+			  IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_SD2_DATA1,
+			  IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_SD2_DATA2,
+			  IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_SD2_DATA3,
+			  IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+
+	out_pad = PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_PULL | PAD_CTL_47K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST;
+	io_pad = PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_47K_PU |
+		PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST;
+
+	mxc_iomux_set_pad(MX51_PIN_SD2_CMD, io_pad);
+	mxc_iomux_set_pad(MX51_PIN_SD2_CLK, out_pad);
+	mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, io_pad);
+	mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, io_pad);
+	mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, io_pad);
+	mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, io_pad);
+}
+#endif
+
 #if defined(CONFIG_FEC_MXC)
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/sys_proto.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/sys_proto.h
index 7b5246e..ce4a94c 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -39,4 +39,9 @@ u32 get_ahb_clk(void);
 u32 get_periph_clk(void);
 char *get_reset_cause(void);
 
+void mx51_uart1_init_pins(void);
+void mx51_ecspi1_init_pins(void);
+void mx51_esdhc1_init_pins(void);
+void mx51_esdhc2_init_pins(void);
+
 #endif

next             reply	other threads:[~2012-08-14 15:46 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-08-14 15:46 Benoît Thébaudeau [this message]
2012-08-14 15:47 ` [U-Boot] [PATCH 2/2] mx5: Use default pin initializers Benoît Thébaudeau
2012-08-15 14:37   ` Benoît Thébaudeau
2012-08-16 19:46   ` Matt Sealey
2012-08-16 20:09     ` Benoît Thébaudeau
2012-08-16 21:25       ` Matt Sealey
2012-08-16 22:51         ` Benoît Thébaudeau
2012-08-17 18:53           ` Matt Sealey
2012-08-17 19:26             ` Benoît Thébaudeau
2012-08-17 21:08         ` Stefano Babic
2012-08-16 20:19     ` Marek Vasut
2012-08-17 19:10 ` [U-Boot] [PATCH 1/2] mx5: Add " Matt Sealey
2012-08-17 19:40   ` Benoît Thébaudeau
2012-08-17 20:25 ` Stefano Babic
2012-08-17 20:38   ` Matt Sealey

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