From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
intel-gfx@lists.freedesktop.org, thomas.daniel@intel.com
Subject: Re: [PATCH] drm/i915: Reset logical ring contexts' head and tail during GPU reset
Date: 16 Feb 2015 19:08:26 -0800 [thread overview]
Message-ID: <898e4a$did77n@FMSMGA003.fm.intel.com> (raw)
In-Reply-To: <1424103173-17387-1-git-send-email-thomas.daniel@intel.com>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5785
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -5 277/277 272/277
ILK 313/313 313/313
SNB -1 309/309 308/309
IVB -1 382/382 381/382
BYT 296/296 296/296
HSW 425/425 425/425
BDW -1 318/318 317/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt_gem_fence_thrash_bo-write-verify-none NRUN(1)PASS(2) FAIL(1)PASS(1)
*PNV igt_gem_fence_thrash_bo-write-verify-x PASS(3) FAIL(1)PASS(1)
*PNV igt_gem_fence_thrash_bo-write-verify-y PASS(3) FAIL(1)PASS(1)
PNV igt_gem_userptr_blits_coherency-sync CRASH(1)PASS(3) CRASH(1)PASS(1)
PNV igt_gem_userptr_blits_coherency-unsync CRASH(1)PASS(2) CRASH(1)PASS(1)
*SNB igt_kms_pipe_crc_basic_read-crc-pipe-A PASS(2) DMESG_WARN(1)PASS(1)
*IVB igt_gem_storedw_batches_loop_normal PASS(3) DMESG_WARN(1)PASS(1)
*BDW igt_gem_gtt_hog PASS(5) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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next prev parent reply other threads:[~2015-02-17 3:23 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-16 16:12 [PATCH] drm/i915: Reset logical ring contexts' head and tail during GPU reset Thomas Daniel
2015-02-17 3:08 ` shuang.he [this message]
2015-02-17 11:34 ` Dave Gordon
2015-02-23 23:21 ` Daniel Vetter
2015-02-23 23:21 ` Daniel Vetter
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