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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-40fb72fb017sm6897468f8f.3.2025.09.26.05.27.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 26 Sep 2025 05:27:15 -0700 (PDT) Message-ID: <89cb92fa-7049-4e41-a34d-29f5ebbcdcab@redhat.com> Date: Fri, 26 Sep 2025 14:27:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 02/14] hw/arm/smmuv3: Correct SMMUEN field name in CR0 To: Tao Tang , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , pierrick.bouvier@linaro.org, philmd@linaro.org, jean-philippe@linaro.org, smostafa@google.com References: <20250925162618.191242-1-tangtao1634@phytium.com.cn> <20250925162618.191242-3-tangtao1634@phytium.com.cn> From: Eric Auger In-Reply-To: <20250925162618.191242-3-tangtao1634@phytium.com.cn> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: z32YhJtzuldHlVi-0r0-fNOk7xQkbr3iYXvDE9-5GL0_1758889637 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.446, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Hi Tao, On 9/25/25 6:26 PM, Tao Tang wrote: > The FIELD macro for the SMMU enable bit in the CR0 register was > incorrectly named SMMU_ENABLE. > > The ARM SMMUv3 Architecture Specification (both older IHI 0070.E.a and > newer IHI 0070.G.b) consistently refers to the SMMU enable bit as SMMUEN. > > This change makes our implementation consistent with the manual. > > Signed-off-by: Tao Tang Reviewed-by: Eric Auger Eric > --- > hw/arm/smmuv3-internal.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index 516f2ffa75..71a3c0c02c 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -116,7 +116,7 @@ REG32(IDR5, 0x14) > REG32(IIDR, 0x18) > REG32(AIDR, 0x1c) > REG32(CR0, 0x20) > - FIELD(CR0, SMMU_ENABLE, 0, 1) > + FIELD(CR0, SMMUEN, 0, 1) > FIELD(CR0, EVENTQEN, 2, 1) > FIELD(CR0, CMDQEN, 3, 1) > > @@ -182,7 +182,7 @@ REG32(EVENTQ_IRQ_CFG2, 0xbc) > > static inline int smmu_enabled(SMMUv3State *s) > { > - return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE); > + return FIELD_EX32(s->cr[0], CR0, SMMUEN); > } > > /* Command Queue Entry */