From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: Clear scanline waits before disabling the pipe. Date: Sun, 08 Aug 2010 19:54:59 +0100 Message-ID: <89kc63$hmibu9@fmsmga002.fm.intel.com> References: <1281265298-29757-1-git-send-email-chris@chris-wilson.co.uk> <878w4h0x9i.fsf@pollan.anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C3719E8BE for ; Sun, 8 Aug 2010 11:55:02 -0700 (PDT) In-Reply-To: <878w4h0x9i.fsf@pollan.anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eric Anholt , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sun, 08 Aug 2010 11:34:01 -0700, Eric Anholt wrote: > On Sun, 8 Aug 2010 12:01:38 +0100, Chris Wilson wrote: > > If we disable the pipe and the GPU is currently waiting on a scanline > > WAIT_FOR_EVENT, the GPU will hang. Fortunately, there is a magic bit > > which we can write on i915+ to break this wait before disabling the > > pipe. > > At one point I thought we were taking the lock and idling the GPU before > a modeset, which would handle this problem, right? This doesn't seem > reliable if we aren't, as we may just have not reached the MI_WAIT_FOR_EVENT > in the ring yet. Hear, hear. I do think this is still racy, but Jesse thought the hardware would do the right thing is could just break the wait and disable the pipe before it had a chance to stall... Actually, I'm not even convinced that the hardware does the right thing if a wait for scanline is executed on a disabled pipe - my headless g45 with a fake output is broken with page-flipping/video. Hmm, might be a worthy addition to hangcheck though to just reset the wait. -- Chris Wilson, Intel Open Source Technology Centre