From mboxrd@z Thu Jan  1 00:00:00 1970
From: Dan Magenheimer <dan.magenheimer@oracle.com>
Subject: [PATCH] pvcpuid: mask TSC invariant bit for various
	circumstances
Date: Mon, 26 Oct 2009 16:12:37 -0700 (PDT)
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pvcpuid: mask TSC invariant bit for PV domains if migration
is not disabled and TSC is not emulated

(Need similar patch for HVM domain)

Signed-off-by: Dan Magenheimer <dan.magenheimer@oracle.com>

diff -r d7d7f978d704 xen/arch/x86/domain.c
--- a/xen/arch/x86/domain.c=09Tue Oct 20 14:36:01 2009 +0100
+++ b/xen/arch/x86/domain.c=09Mon Oct 26 16:13:43 2009 -0600
@@ -51,6 +51,7 @@
 #include <asm/nmi.h>
 #include <xen/numa.h>
 #include <xen/iommu.h>
+#include <public/arch-x86/cpuid.h>
 #ifdef CONFIG_COMPAT
 #include <compat/vcpu.h>
 #endif
@@ -2044,6 +2045,13 @@ void domain_cpuid(
             *ebx =3D cpuid->ebx;
             *ecx =3D cpuid->ecx;
             *edx =3D cpuid->edx;
+            if ( input =3D=3D XEN_CPUID_APM_FUNCTION )
+            {
+                /* mask TSC invariant bit if migration is not disabled
+                   and TSC is not emulated */
+                if ( !d->disable_migrate && !d->arch.vtsc )
+                    *edx &=3D ~XEN_CPUID_APM_EDX_TSC_INVARIANT;
+            }
             return;
         }
     }
diff -r d7d7f978d704 xen/include/public/arch-x86/cpuid.h
--- a/xen/include/public/arch-x86/cpuid.h=09Tue Oct 20 14:36:01 2009 +0100
+++ b/xen/include/public/arch-x86/cpuid.h=09Mon Oct 26 16:13:43 2009 -0600
@@ -65,4 +65,8 @@
 #define _XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD 0
 #define XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD  (1u<<0)
=20
+/* Does the host support TSC Invariance (in Advanced Power Management)? */
+#define XEN_CPUID_APM_FUNCTION          0x80000007
+#define XEN_CPUID_APM_EDX_TSC_INVARIANT (1u<<8)
+
 #endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */

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