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([2001:4c4e:24d7:a100:a3f1:d8a2:d12f:314d]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-25c3a84a744sm64511285ad.74.2025.09.12.22.27.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Sep 2025 22:28:00 -0700 (PDT) Message-ID: <8acbb3b27a933b60b17b06a03454cc171f1cefc8.camel@gmail.com> Subject: Re: [PATCH 3/5] drm/amdgpu/sdma5.2: adjust SDMA limits From: timur.kristof@gmail.com To: Alex Deucher , Alex Deucher Cc: amd-gfx@lists.freedesktop.org, christian.koenig@amd.com Date: Sat, 13 Sep 2025 07:27:53 +0200 In-Reply-To: References: <20250911172449.3340848-1-alexander.deucher@amd.com> <20250911172449.3340848-3-alexander.deucher@amd.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) MIME-Version: 1.0 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Fri, 2025-09-12 at 15:38 -0400, Alex Deucher wrote: > On Thu, Sep 11, 2025 at 2:18=E2=80=AFPM Alex Deucher > wrote: > >=20 > > On Thu, Sep 11, 2025 at 1:25=E2=80=AFPM Alex Deucher > > wrote: > > >=20 > > > SDMA 5.2.x has increased transfer limits. > > >=20 > > > v2: fix harder, use shifts to make it more obvious > > >=20 > > > Signed-off-by: Alex Deucher > > > --- > > > =C2=A0drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++-- > > > =C2=A01 file changed, 2 insertions(+), 2 deletions(-) > > >=20 > > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > > > b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > > > index a8e39df29f343..bf227eadbe487 100644 > > > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > > > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > > > @@ -2065,11 +2065,11 @@ static void > > > sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, > > > =C2=A0} > > >=20 > > > =C2=A0static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = =3D > > > { > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .copy_max_bytes =3D 0x400000, > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .copy_max_bytes =3D 1 << 30, > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .copy_num_dw =3D 7, > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .emit_copy_buffer =3D sdma= _v5_2_emit_copy_buffer, > > >=20 > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .fill_max_bytes =3D 0x400000, > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .fill_max_bytes =3D 1 << 30, > >=20 > > The hw docs and PAL differ here.=C2=A0 I've asked the hw designers to > > clarify. >=20 > The HW team verified that the hardware supports the extended range > for > both copies and fills. >=20 > Alex Hi Alex, This is still pretty confusing. According to PAL, only SDMA v6 has the extended range for fills, and it can do 4 bytes fewer. Are you sure that PAL is wrong about this? For reference: https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/gfx1= 0/gfx10DmaCmdBuffer.cpp https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/hw/gfxip/sdma/gfx1= 2/gfx12DmaCmdBuffer.cpp MaxCopySize on GFX10: 1 << 22 MaxCopySize on GFX10.3+: 1 << 30 MaxFillSize on GFX10-10.3: (1 << 22 - 1) & ~3 MaxFillSize on GFX11+: (1 << 30 - 1) & ~3 This makes sense because they program the count field in the packet using the byte count minus four. Thanks, Timur