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Wed, 24 Jul 2024 17:55:30 +0200 Message-ID: <8c4e26f5-cf28-44f6-8b76-c80832cfe1a2@gmx.net> Date: Wed, 24 Jul 2024 17:55:29 +0200 Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: mx93: No cache hierachy definitions for ARM cores To: Sudeep Holla Cc: Frank Li , Fabio Estevam , peng.fan@nxp.com, peng.fan@oss.nxp.com, Shawn Guo , Sascha Hauer , imx@lists.linux.dev, Pengutronix Kernel Team , Linux ARM References: Content-Language: en-US From: Stefan Wahren In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:u8HU8INS77uJ7wVQJy9DjbK0xl5kuhAg7jviEk6/Qt+3eg19KYd FpOD6r4QuIU0ifi1xWl+rMWD5y/vi70YceJdqU/CZhRgtF24R5ZV2ec7QKT4avFoIVHs/SA e8+zv2KW/Jfgl0MzYWS1z2bBvdkKIpAXTjvl0jLaUC21wS/4NynnyqwHuPCb5v5ohfsgrGT 8n1QuSRCzr/jjNx2mNCBg== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:cNS7v/nWr3Y=;lozkfBaF0a6+jvrnL9AC7FXI+NB s5S3SkgMZSE6IFZm3MZDK+RRSk2350+OjNggO/OlY2UCufb4y1f2eMPszYyJS4eWzUm32r3Gt MrMIWLSpfeg7E32T+VqaMCRaFyJZyzDoKWHuDci0SXnSDNEB9Px/YoyJWqjghDGfkRH2OOisx awMECsF5WJ2ZQ1S5iXk21LXFgROJ898hy3uxM2nLIIPRPrFsnV0znocmOEkisNOd4s1qFeBq2 fSDiJoFSepw0AFHv1v0uBMAekN7SSoJqi2wTxLpSJ95VjD/798tZlax/iokzc2q1q8NOiWTHB YotOZmVGtqIBDboHZVsHPSN2PamFFMHN2P7hyOi7DUk8lqdCOJxefYGPHo2hlJrap1VJExNru lVmG+c2wnC7FGFE/5i1/ONC7K5FJ5jClNnRF4WcC5o1HJtUxZy4xxQQsAPj/WyPXiNSEsMrPT sxGtck1rRYcQ+mu2H1t9BEWFmfaZB+0RGv1SKZWtLUnuYf4mHctbcFMuZwqaNrsJrbzbCzAFi L+4ixi5DxhgiArIA0s8W5lmDobdkluCY31XKrNFBkspaEw1D22XbDJG49+zf9h36ZjRiv/E5U 44CPXtNLfe9MphkV+zpuBYMkqJ/U9O/ImuqEYAN5AHycZIEUeatvex73tKplHWwits8RJR5h6 pHPZGwhWH+31PO/rN9I1W8fPVIbsNMaMfF52vpGh59pCq4N2/r9X2drZcwxsQFqiZeP7FGb5A MsMlmLS+Ti+N7+foDZr7W9BXqKLIb3IFEO62+Z+bOr6uXYmBD+2o5uIL/jmNb+/h+n6VwMkCy 0y5H22UE3xr7ieSk19GBPnNA1cO7gwZ8UK7bN+KFhiMNY= Am 24.07.24 um 16:34 schrieb Sudeep Holla: > On Wed, Jul 24, 2024 at 11:48:13AM +0200, Stefan Wahren wrote: >> Hi Frank, >> >> Am 19.07.24 um 16:52 schrieb Frank Li: >>> On Thu, Jul 18, 2024 at 11:38:20PM -0300, Fabio Estevam wrote: >>>> On Wed, Jul 17, 2024 at 2:49=E2=80=AFPM Stefan Wahren wrote: >>>>> Hi, >>>>> today i noticed that imx93.dtsi lacks the cache definitions for the >>>>> Cortex-A55 cores: >>>>> >>>>> cacheinfo: Unable to detect cache hierarchy for CPU 0 >>>>> >>>>> Maybe someone with more insight can add this to the imx93.dtsi file. >>>> Frank, can you help? >>> Peng: >>> Some informatin missed at public RM. Can you help this? I found >>> it also missed in internal tree. >> does the official ARM documentation [1] provide the missing information= ? >> >> [1] - https://developer.arm.com/documentation/101051/0101 > I assume you meant [2] instead of [1], as Cortex A55 and M55 are differe= nt. Sorry, you are absolutely right. > > -- > Regards, > Sudeep > > [2] https://developer.arm.com/documentation/100442/0200/