From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE016C71157 for ; Wed, 18 Jun 2025 07:46:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4O0/leIsBfJLkIF52UvDIYaiXpPW3+u6JnGeyfyG0uU=; b=qwWPTlto4V2Ia+ Qbuf7RBGr7w/ySPodTnuAsPBPCoBjrHxh3Upy6MCo2JTjDYILQ9aE+3l+jkLoh4RiwSDbh1oVM/WM gfOuzSwYv5WWZHwnY2WgiXBwGQPXwy8Xj/AUxEvd1XQ0rWoo6yXXj/gtvWfIBiogvCAdrDTP4sAYr Z2LiFgIfsMorzg+lLJmLNN9MCTuF6hwDJSznObuoS4RFoi043y3VWn/TEdDzyb31aTcKN0ValFNIM MZkI1D4gQcUzUoeN4/knomYu/AyJmMtJJRsqk14TZkMXapPPe7R3lTSgYuEb7ZIUGjEYIw6T3k+Rw YIKm+z/AxPlsEqzPeMGw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uRnVK-00000009K4v-1R97; Wed, 18 Jun 2025 07:46:42 +0000 Received: from out-188.mta1.migadu.com ([2001:41d0:203:375::bc]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uRmU1-00000009CYW-2sv8 for kvm-riscv@lists.infradead.org; Wed, 18 Jun 2025 06:41:19 +0000 Message-ID: <8c51685c-de2f-48ed-b0b6-87ac44073684@linux.dev> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750228874; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Vx7JDHQ6srbDcbhQvBkA6hELvFYIhF9e9poQ0xOUOKU=; b=LSVfc6SsSY39VUCNHIgJHBxVAduEis1okaYmqlEta/beC6pWCMHiDXb8ENn+9cgxXfbWDc mq9E4uQsWEQGw70tjcMYaxay4likm+RkUbuzfA4s1apaPUs/SsGEgQXdps85zHQFD0W9DR iTs3i3xvcTYC+aiGX2yUt+C6iWk6Zfs= Date: Tue, 17 Jun 2025 23:41:08 -0700 MIME-Version: 1.0 Subject: Re: [PATCH v2 08/12] RISC-V: KVM: Factor-out MMU related declarations into separate headers To: Anup Patel Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250613065743.737102-1-apatel@ventanamicro.com> <20250613065743.737102-9-apatel@ventanamicro.com> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Atish Patra In-Reply-To: <20250613065743.737102-9-apatel@ventanamicro.com> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250617_234118_160883_DDDD750E X-CRM114-Status: GOOD ( 18.68 ) X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+kvm-riscv=archiver.kernel.org@lists.infradead.org On 6/12/25 11:57 PM, Anup Patel wrote: > The MMU, TLB, and VMID management for KVM RISC-V already exists as > seprate sources so create separate headers along these lines. This > further simplifies asm/kvm_host.h header. > > Signed-off-by: Anup Patel > --- > arch/riscv/include/asm/kvm_host.h | 100 +----------------------------- > arch/riscv/include/asm/kvm_mmu.h | 26 ++++++++ > arch/riscv/include/asm/kvm_tlb.h | 78 +++++++++++++++++++++++ > arch/riscv/include/asm/kvm_vmid.h | 27 ++++++++ > arch/riscv/kvm/aia_imsic.c | 1 + > arch/riscv/kvm/main.c | 1 + > arch/riscv/kvm/mmu.c | 1 + > arch/riscv/kvm/tlb.c | 2 + > arch/riscv/kvm/vcpu.c | 1 + > arch/riscv/kvm/vcpu_exit.c | 1 + > arch/riscv/kvm/vm.c | 1 + > arch/riscv/kvm/vmid.c | 2 + > 12 files changed, 143 insertions(+), 98 deletions(-) > create mode 100644 arch/riscv/include/asm/kvm_mmu.h > create mode 100644 arch/riscv/include/asm/kvm_tlb.h > create mode 100644 arch/riscv/include/asm/kvm_vmid.h > > diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h > index 6162575e2177..bd5341efa127 100644 > --- a/arch/riscv/include/asm/kvm_host.h > +++ b/arch/riscv/include/asm/kvm_host.h > @@ -16,6 +16,8 @@ > #include > #include > #include > +#include > +#include > #include > #include > #include > @@ -56,24 +58,6 @@ > BIT(IRQ_VS_TIMER) | \ > BIT(IRQ_VS_EXT)) > > -enum kvm_riscv_hfence_type { > - KVM_RISCV_HFENCE_UNKNOWN = 0, > - KVM_RISCV_HFENCE_GVMA_VMID_GPA, > - KVM_RISCV_HFENCE_VVMA_ASID_GVA, > - KVM_RISCV_HFENCE_VVMA_ASID_ALL, > - KVM_RISCV_HFENCE_VVMA_GVA, > -}; > - > -struct kvm_riscv_hfence { > - enum kvm_riscv_hfence_type type; > - unsigned long asid; > - unsigned long order; > - gpa_t addr; > - gpa_t size; > -}; > - > -#define KVM_RISCV_VCPU_MAX_HFENCE 64 > - > struct kvm_vm_stat { > struct kvm_vm_stat_generic generic; > }; > @@ -99,15 +83,6 @@ struct kvm_vcpu_stat { > struct kvm_arch_memory_slot { > }; > > -struct kvm_vmid { > - /* > - * Writes to vmid_version and vmid happen with vmid_lock held > - * whereas reads happen without any lock held. > - */ > - unsigned long vmid_version; > - unsigned long vmid; > -}; > - > struct kvm_arch { > /* G-stage vmid */ > struct kvm_vmid vmid; > @@ -311,77 +286,6 @@ static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) > return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; > } > > -#define KVM_RISCV_GSTAGE_TLB_MIN_ORDER 12 > - > -void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, > - gpa_t gpa, gpa_t gpsz, > - unsigned long order); > -void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid); > -void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz, > - unsigned long order); > -void kvm_riscv_local_hfence_gvma_all(void); > -void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid, > - unsigned long asid, > - unsigned long gva, > - unsigned long gvsz, > - unsigned long order); > -void kvm_riscv_local_hfence_vvma_asid_all(unsigned long vmid, > - unsigned long asid); > -void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid, > - unsigned long gva, unsigned long gvsz, > - unsigned long order); > -void kvm_riscv_local_hfence_vvma_all(unsigned long vmid); > - > -void kvm_riscv_tlb_flush_process(struct kvm_vcpu *vcpu); > - > -void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu); > -void kvm_riscv_hfence_vvma_all_process(struct kvm_vcpu *vcpu); > -void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu); > - > -void kvm_riscv_fence_i(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask); > -void kvm_riscv_hfence_gvma_vmid_gpa(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask, > - gpa_t gpa, gpa_t gpsz, > - unsigned long order); > -void kvm_riscv_hfence_gvma_vmid_all(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask); > -void kvm_riscv_hfence_vvma_asid_gva(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask, > - unsigned long gva, unsigned long gvsz, > - unsigned long order, unsigned long asid); > -void kvm_riscv_hfence_vvma_asid_all(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask, > - unsigned long asid); > -void kvm_riscv_hfence_vvma_gva(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask, > - unsigned long gva, unsigned long gvsz, > - unsigned long order); > -void kvm_riscv_hfence_vvma_all(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask); > - > -int kvm_riscv_gstage_ioremap(struct kvm *kvm, gpa_t gpa, > - phys_addr_t hpa, unsigned long size, > - bool writable, bool in_atomic); > -void kvm_riscv_gstage_iounmap(struct kvm *kvm, gpa_t gpa, > - unsigned long size); > -int kvm_riscv_gstage_map(struct kvm_vcpu *vcpu, > - struct kvm_memory_slot *memslot, > - gpa_t gpa, unsigned long hva, bool is_write); > -int kvm_riscv_gstage_alloc_pgd(struct kvm *kvm); > -void kvm_riscv_gstage_free_pgd(struct kvm *kvm); > -void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu); > -void __init kvm_riscv_gstage_mode_detect(void); > -unsigned long __init kvm_riscv_gstage_mode(void); > -int kvm_riscv_gstage_gpa_bits(void); > - > -void __init kvm_riscv_gstage_vmid_detect(void); > -unsigned long kvm_riscv_gstage_vmid_bits(void); > -int kvm_riscv_gstage_vmid_init(struct kvm *kvm); > -bool kvm_riscv_gstage_vmid_ver_changed(struct kvm_vmid *vmid); > -void kvm_riscv_gstage_vmid_update(struct kvm_vcpu *vcpu); > -void kvm_riscv_gstage_vmid_sanitize(struct kvm_vcpu *vcpu); > - > int kvm_riscv_setup_default_irq_routing(struct kvm *kvm, u32 lines); > > void __kvm_riscv_unpriv_trap(void); > diff --git a/arch/riscv/include/asm/kvm_mmu.h b/arch/riscv/include/asm/kvm_mmu.h > new file mode 100644 > index 000000000000..4e1654282ee4 > --- /dev/null > +++ b/arch/riscv/include/asm/kvm_mmu.h > @@ -0,0 +1,26 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2025 Ventana Micro Systems Inc. > + */ > + > +#ifndef __RISCV_KVM_MMU_H_ > +#define __RISCV_KVM_MMU_H_ > + > +#include > + > +int kvm_riscv_gstage_ioremap(struct kvm *kvm, gpa_t gpa, > + phys_addr_t hpa, unsigned long size, > + bool writable, bool in_atomic); > +void kvm_riscv_gstage_iounmap(struct kvm *kvm, gpa_t gpa, > + unsigned long size); > +int kvm_riscv_gstage_map(struct kvm_vcpu *vcpu, > + struct kvm_memory_slot *memslot, > + gpa_t gpa, unsigned long hva, bool is_write); > +int kvm_riscv_gstage_alloc_pgd(struct kvm *kvm); > +void kvm_riscv_gstage_free_pgd(struct kvm *kvm); > +void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu); > +void kvm_riscv_gstage_mode_detect(void); > +unsigned long kvm_riscv_gstage_mode(void); > +int kvm_riscv_gstage_gpa_bits(void); > + > +#endif > diff --git a/arch/riscv/include/asm/kvm_tlb.h b/arch/riscv/include/asm/kvm_tlb.h > new file mode 100644 > index 000000000000..cd00c9a46cb1 > --- /dev/null > +++ b/arch/riscv/include/asm/kvm_tlb.h > @@ -0,0 +1,78 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2025 Ventana Micro Systems Inc. > + */ > + > +#ifndef __RISCV_KVM_TLB_H_ > +#define __RISCV_KVM_TLB_H_ > + > +#include > + > +enum kvm_riscv_hfence_type { > + KVM_RISCV_HFENCE_UNKNOWN = 0, > + KVM_RISCV_HFENCE_GVMA_VMID_GPA, > + KVM_RISCV_HFENCE_VVMA_ASID_GVA, > + KVM_RISCV_HFENCE_VVMA_ASID_ALL, > + KVM_RISCV_HFENCE_VVMA_GVA, > +}; > + > +struct kvm_riscv_hfence { > + enum kvm_riscv_hfence_type type; > + unsigned long asid; > + unsigned long order; > + gpa_t addr; > + gpa_t size; > +}; > + > +#define KVM_RISCV_VCPU_MAX_HFENCE 64 > + > +#define KVM_RISCV_GSTAGE_TLB_MIN_ORDER 12 > + > +void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, > + gpa_t gpa, gpa_t gpsz, > + unsigned long order); > +void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid); > +void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz, > + unsigned long order); > +void kvm_riscv_local_hfence_gvma_all(void); > +void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid, > + unsigned long asid, > + unsigned long gva, > + unsigned long gvsz, > + unsigned long order); > +void kvm_riscv_local_hfence_vvma_asid_all(unsigned long vmid, > + unsigned long asid); > +void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid, > + unsigned long gva, unsigned long gvsz, > + unsigned long order); > +void kvm_riscv_local_hfence_vvma_all(unsigned long vmid); > + > +void kvm_riscv_tlb_flush_process(struct kvm_vcpu *vcpu); > + > +void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu); > +void kvm_riscv_hfence_vvma_all_process(struct kvm_vcpu *vcpu); > +void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu); > + > +void kvm_riscv_fence_i(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask); > +void kvm_riscv_hfence_gvma_vmid_gpa(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask, > + gpa_t gpa, gpa_t gpsz, > + unsigned long order); > +void kvm_riscv_hfence_gvma_vmid_all(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask); > +void kvm_riscv_hfence_vvma_asid_gva(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask, > + unsigned long gva, unsigned long gvsz, > + unsigned long order, unsigned long asid); > +void kvm_riscv_hfence_vvma_asid_all(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask, > + unsigned long asid); > +void kvm_riscv_hfence_vvma_gva(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask, > + unsigned long gva, unsigned long gvsz, > + unsigned long order); > +void kvm_riscv_hfence_vvma_all(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask); > + > +#endif > diff --git a/arch/riscv/include/asm/kvm_vmid.h b/arch/riscv/include/asm/kvm_vmid.h > new file mode 100644 > index 000000000000..ab98e1434fb7 > --- /dev/null > +++ b/arch/riscv/include/asm/kvm_vmid.h > @@ -0,0 +1,27 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2025 Ventana Micro Systems Inc. > + */ > + > +#ifndef __RISCV_KVM_VMID_H_ > +#define __RISCV_KVM_VMID_H_ > + > +#include > + > +struct kvm_vmid { > + /* > + * Writes to vmid_version and vmid happen with vmid_lock held > + * whereas reads happen without any lock held. > + */ > + unsigned long vmid_version; > + unsigned long vmid; > +}; > + > +void __init kvm_riscv_gstage_vmid_detect(void); > +unsigned long kvm_riscv_gstage_vmid_bits(void); > +int kvm_riscv_gstage_vmid_init(struct kvm *kvm); > +bool kvm_riscv_gstage_vmid_ver_changed(struct kvm_vmid *vmid); > +void kvm_riscv_gstage_vmid_update(struct kvm_vcpu *vcpu); > +void kvm_riscv_gstage_vmid_sanitize(struct kvm_vcpu *vcpu); > + > +#endif > diff --git a/arch/riscv/kvm/aia_imsic.c b/arch/riscv/kvm/aia_imsic.c > index 29ef9c2133a9..40b469c0a01f 100644 > --- a/arch/riscv/kvm/aia_imsic.c > +++ b/arch/riscv/kvm/aia_imsic.c > @@ -16,6 +16,7 @@ > #include > #include > #include > +#include > > #define IMSIC_MAX_EIX (IMSIC_MAX_ID / BITS_PER_TYPE(u64)) > > diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c > index 4b24705dc63a..b861a5dd7bd9 100644 > --- a/arch/riscv/kvm/main.c > +++ b/arch/riscv/kvm/main.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > #include > #include > > diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c > index a5387927a1c1..c1a3eb076df3 100644 > --- a/arch/riscv/kvm/mmu.c > +++ b/arch/riscv/kvm/mmu.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include > #include > diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c > index f46a27658c2e..6fc4361c3d75 100644 > --- a/arch/riscv/kvm/tlb.c > +++ b/arch/riscv/kvm/tlb.c > @@ -15,6 +15,8 @@ > #include > #include > #include > +#include > +#include > > #define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) > > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > index 6eb11c913b13..8ad7b31f5939 100644 > --- a/arch/riscv/kvm/vcpu.c > +++ b/arch/riscv/kvm/vcpu.c > @@ -18,6 +18,7 @@ > #include > #include > #include > +#include > #include > #include > > diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c > index 85c43c83e3b9..965df528de90 100644 > --- a/arch/riscv/kvm/vcpu_exit.c > +++ b/arch/riscv/kvm/vcpu_exit.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > #include > > static int gstage_page_fault(struct kvm_vcpu *vcpu, struct kvm_run *run, > diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c > index b27ec8f96697..8601cf29e5f8 100644 > --- a/arch/riscv/kvm/vm.c > +++ b/arch/riscv/kvm/vm.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > > const struct _kvm_stats_desc kvm_vm_stats_desc[] = { > KVM_GENERIC_VM_STATS() > diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c > index 92c01255f86f..3b426c800480 100644 > --- a/arch/riscv/kvm/vmid.c > +++ b/arch/riscv/kvm/vmid.c > @@ -14,6 +14,8 @@ > #include > #include > #include > +#include > +#include > > static unsigned long vmid_version = 1; > static unsigned long vmid_next; LGTM. Reviewed-by: Atish Patra -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-176.mta1.migadu.com (out-176.mta1.migadu.com [95.215.58.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D093F20C480 for ; Wed, 18 Jun 2025 06:41:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.176 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750228891; cv=none; b=LNIf3xBK0OSh80estGCwqFBspZxFah/6IUg0gv76AUBRlKlj0ATlrwndKPyxWNKWlQlJSp0QV3O2H+0GAY4zyUP8QzNVrO41ktBIzt52kjr0L6FdziO1fthPSQpHTgOAwlD9s5ieWvz5ta1OvmBRTY3gVAgjU7WS24VxqB132nQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750228891; c=relaxed/simple; bh=M/l30/IRoenHGy5VzSUsqFROULvVyK5iMYOn2/mDCaM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=s+pL07KzFXivHINCwGOYnhWisncWFMM2MEN4H22YmXpX0HPANhCGt6DVW8iykCpvH9r40nT4lAuSdyh325MPT6leOC0mSeFQn3fMBtD6F54LddYTQdGFrrJQkLygk5ruAg6PDVc5NH82rPU5UCJ6ArPsmhCQ7VdLfbtjB2nkubs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=LSVfc6Ss; arc=none smtp.client-ip=95.215.58.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="LSVfc6Ss" Message-ID: <8c51685c-de2f-48ed-b0b6-87ac44073684@linux.dev> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750228874; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Vx7JDHQ6srbDcbhQvBkA6hELvFYIhF9e9poQ0xOUOKU=; b=LSVfc6SsSY39VUCNHIgJHBxVAduEis1okaYmqlEta/beC6pWCMHiDXb8ENn+9cgxXfbWDc mq9E4uQsWEQGw70tjcMYaxay4likm+RkUbuzfA4s1apaPUs/SsGEgQXdps85zHQFD0W9DR iTs3i3xvcTYC+aiGX2yUt+C6iWk6Zfs= Date: Tue, 17 Jun 2025 23:41:08 -0700 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v2 08/12] RISC-V: KVM: Factor-out MMU related declarations into separate headers To: Anup Patel Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250613065743.737102-1-apatel@ventanamicro.com> <20250613065743.737102-9-apatel@ventanamicro.com> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Atish Patra In-Reply-To: <20250613065743.737102-9-apatel@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Migadu-Flow: FLOW_OUT On 6/12/25 11:57 PM, Anup Patel wrote: > The MMU, TLB, and VMID management for KVM RISC-V already exists as > seprate sources so create separate headers along these lines. This > further simplifies asm/kvm_host.h header. > > Signed-off-by: Anup Patel > --- > arch/riscv/include/asm/kvm_host.h | 100 +----------------------------- > arch/riscv/include/asm/kvm_mmu.h | 26 ++++++++ > arch/riscv/include/asm/kvm_tlb.h | 78 +++++++++++++++++++++++ > arch/riscv/include/asm/kvm_vmid.h | 27 ++++++++ > arch/riscv/kvm/aia_imsic.c | 1 + > arch/riscv/kvm/main.c | 1 + > arch/riscv/kvm/mmu.c | 1 + > arch/riscv/kvm/tlb.c | 2 + > arch/riscv/kvm/vcpu.c | 1 + > arch/riscv/kvm/vcpu_exit.c | 1 + > arch/riscv/kvm/vm.c | 1 + > arch/riscv/kvm/vmid.c | 2 + > 12 files changed, 143 insertions(+), 98 deletions(-) > create mode 100644 arch/riscv/include/asm/kvm_mmu.h > create mode 100644 arch/riscv/include/asm/kvm_tlb.h > create mode 100644 arch/riscv/include/asm/kvm_vmid.h > > diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h > index 6162575e2177..bd5341efa127 100644 > --- a/arch/riscv/include/asm/kvm_host.h > +++ b/arch/riscv/include/asm/kvm_host.h > @@ -16,6 +16,8 @@ > #include > #include > #include > +#include > +#include > #include > #include > #include > @@ -56,24 +58,6 @@ > BIT(IRQ_VS_TIMER) | \ > BIT(IRQ_VS_EXT)) > > -enum kvm_riscv_hfence_type { > - KVM_RISCV_HFENCE_UNKNOWN = 0, > - KVM_RISCV_HFENCE_GVMA_VMID_GPA, > - KVM_RISCV_HFENCE_VVMA_ASID_GVA, > - KVM_RISCV_HFENCE_VVMA_ASID_ALL, > - KVM_RISCV_HFENCE_VVMA_GVA, > -}; > - > -struct kvm_riscv_hfence { > - enum kvm_riscv_hfence_type type; > - unsigned long asid; > - unsigned long order; > - gpa_t addr; > - gpa_t size; > -}; > - > -#define KVM_RISCV_VCPU_MAX_HFENCE 64 > - > struct kvm_vm_stat { > struct kvm_vm_stat_generic generic; > }; > @@ -99,15 +83,6 @@ struct kvm_vcpu_stat { > struct kvm_arch_memory_slot { > }; > > -struct kvm_vmid { > - /* > - * Writes to vmid_version and vmid happen with vmid_lock held > - * whereas reads happen without any lock held. > - */ > - unsigned long vmid_version; > - unsigned long vmid; > -}; > - > struct kvm_arch { > /* G-stage vmid */ > struct kvm_vmid vmid; > @@ -311,77 +286,6 @@ static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) > return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; > } > > -#define KVM_RISCV_GSTAGE_TLB_MIN_ORDER 12 > - > -void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, > - gpa_t gpa, gpa_t gpsz, > - unsigned long order); > -void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid); > -void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz, > - unsigned long order); > -void kvm_riscv_local_hfence_gvma_all(void); > -void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid, > - unsigned long asid, > - unsigned long gva, > - unsigned long gvsz, > - unsigned long order); > -void kvm_riscv_local_hfence_vvma_asid_all(unsigned long vmid, > - unsigned long asid); > -void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid, > - unsigned long gva, unsigned long gvsz, > - unsigned long order); > -void kvm_riscv_local_hfence_vvma_all(unsigned long vmid); > - > -void kvm_riscv_tlb_flush_process(struct kvm_vcpu *vcpu); > - > -void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu); > -void kvm_riscv_hfence_vvma_all_process(struct kvm_vcpu *vcpu); > -void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu); > - > -void kvm_riscv_fence_i(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask); > -void kvm_riscv_hfence_gvma_vmid_gpa(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask, > - gpa_t gpa, gpa_t gpsz, > - unsigned long order); > -void kvm_riscv_hfence_gvma_vmid_all(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask); > -void kvm_riscv_hfence_vvma_asid_gva(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask, > - unsigned long gva, unsigned long gvsz, > - unsigned long order, unsigned long asid); > -void kvm_riscv_hfence_vvma_asid_all(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask, > - unsigned long asid); > -void kvm_riscv_hfence_vvma_gva(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask, > - unsigned long gva, unsigned long gvsz, > - unsigned long order); > -void kvm_riscv_hfence_vvma_all(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask); > - > -int kvm_riscv_gstage_ioremap(struct kvm *kvm, gpa_t gpa, > - phys_addr_t hpa, unsigned long size, > - bool writable, bool in_atomic); > -void kvm_riscv_gstage_iounmap(struct kvm *kvm, gpa_t gpa, > - unsigned long size); > -int kvm_riscv_gstage_map(struct kvm_vcpu *vcpu, > - struct kvm_memory_slot *memslot, > - gpa_t gpa, unsigned long hva, bool is_write); > -int kvm_riscv_gstage_alloc_pgd(struct kvm *kvm); > -void kvm_riscv_gstage_free_pgd(struct kvm *kvm); > -void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu); > -void __init kvm_riscv_gstage_mode_detect(void); > -unsigned long __init kvm_riscv_gstage_mode(void); > -int kvm_riscv_gstage_gpa_bits(void); > - > -void __init kvm_riscv_gstage_vmid_detect(void); > -unsigned long kvm_riscv_gstage_vmid_bits(void); > -int kvm_riscv_gstage_vmid_init(struct kvm *kvm); > -bool kvm_riscv_gstage_vmid_ver_changed(struct kvm_vmid *vmid); > -void kvm_riscv_gstage_vmid_update(struct kvm_vcpu *vcpu); > -void kvm_riscv_gstage_vmid_sanitize(struct kvm_vcpu *vcpu); > - > int kvm_riscv_setup_default_irq_routing(struct kvm *kvm, u32 lines); > > void __kvm_riscv_unpriv_trap(void); > diff --git a/arch/riscv/include/asm/kvm_mmu.h b/arch/riscv/include/asm/kvm_mmu.h > new file mode 100644 > index 000000000000..4e1654282ee4 > --- /dev/null > +++ b/arch/riscv/include/asm/kvm_mmu.h > @@ -0,0 +1,26 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2025 Ventana Micro Systems Inc. > + */ > + > +#ifndef __RISCV_KVM_MMU_H_ > +#define __RISCV_KVM_MMU_H_ > + > +#include > + > +int kvm_riscv_gstage_ioremap(struct kvm *kvm, gpa_t gpa, > + phys_addr_t hpa, unsigned long size, > + bool writable, bool in_atomic); > +void kvm_riscv_gstage_iounmap(struct kvm *kvm, gpa_t gpa, > + unsigned long size); > +int kvm_riscv_gstage_map(struct kvm_vcpu *vcpu, > + struct kvm_memory_slot *memslot, > + gpa_t gpa, unsigned long hva, bool is_write); > +int kvm_riscv_gstage_alloc_pgd(struct kvm *kvm); > +void kvm_riscv_gstage_free_pgd(struct kvm *kvm); > +void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu); > +void kvm_riscv_gstage_mode_detect(void); > +unsigned long kvm_riscv_gstage_mode(void); > +int kvm_riscv_gstage_gpa_bits(void); > + > +#endif > diff --git a/arch/riscv/include/asm/kvm_tlb.h b/arch/riscv/include/asm/kvm_tlb.h > new file mode 100644 > index 000000000000..cd00c9a46cb1 > --- /dev/null > +++ b/arch/riscv/include/asm/kvm_tlb.h > @@ -0,0 +1,78 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2025 Ventana Micro Systems Inc. > + */ > + > +#ifndef __RISCV_KVM_TLB_H_ > +#define __RISCV_KVM_TLB_H_ > + > +#include > + > +enum kvm_riscv_hfence_type { > + KVM_RISCV_HFENCE_UNKNOWN = 0, > + KVM_RISCV_HFENCE_GVMA_VMID_GPA, > + KVM_RISCV_HFENCE_VVMA_ASID_GVA, > + KVM_RISCV_HFENCE_VVMA_ASID_ALL, > + KVM_RISCV_HFENCE_VVMA_GVA, > +}; > + > +struct kvm_riscv_hfence { > + enum kvm_riscv_hfence_type type; > + unsigned long asid; > + unsigned long order; > + gpa_t addr; > + gpa_t size; > +}; > + > +#define KVM_RISCV_VCPU_MAX_HFENCE 64 > + > +#define KVM_RISCV_GSTAGE_TLB_MIN_ORDER 12 > + > +void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, > + gpa_t gpa, gpa_t gpsz, > + unsigned long order); > +void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid); > +void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz, > + unsigned long order); > +void kvm_riscv_local_hfence_gvma_all(void); > +void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid, > + unsigned long asid, > + unsigned long gva, > + unsigned long gvsz, > + unsigned long order); > +void kvm_riscv_local_hfence_vvma_asid_all(unsigned long vmid, > + unsigned long asid); > +void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid, > + unsigned long gva, unsigned long gvsz, > + unsigned long order); > +void kvm_riscv_local_hfence_vvma_all(unsigned long vmid); > + > +void kvm_riscv_tlb_flush_process(struct kvm_vcpu *vcpu); > + > +void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu); > +void kvm_riscv_hfence_vvma_all_process(struct kvm_vcpu *vcpu); > +void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu); > + > +void kvm_riscv_fence_i(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask); > +void kvm_riscv_hfence_gvma_vmid_gpa(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask, > + gpa_t gpa, gpa_t gpsz, > + unsigned long order); > +void kvm_riscv_hfence_gvma_vmid_all(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask); > +void kvm_riscv_hfence_vvma_asid_gva(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask, > + unsigned long gva, unsigned long gvsz, > + unsigned long order, unsigned long asid); > +void kvm_riscv_hfence_vvma_asid_all(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask, > + unsigned long asid); > +void kvm_riscv_hfence_vvma_gva(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask, > + unsigned long gva, unsigned long gvsz, > + unsigned long order); > +void kvm_riscv_hfence_vvma_all(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask); > + > +#endif > diff --git a/arch/riscv/include/asm/kvm_vmid.h b/arch/riscv/include/asm/kvm_vmid.h > new file mode 100644 > index 000000000000..ab98e1434fb7 > --- /dev/null > +++ b/arch/riscv/include/asm/kvm_vmid.h > @@ -0,0 +1,27 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2025 Ventana Micro Systems Inc. > + */ > + > +#ifndef __RISCV_KVM_VMID_H_ > +#define __RISCV_KVM_VMID_H_ > + > +#include > + > +struct kvm_vmid { > + /* > + * Writes to vmid_version and vmid happen with vmid_lock held > + * whereas reads happen without any lock held. > + */ > + unsigned long vmid_version; > + unsigned long vmid; > +}; > + > +void __init kvm_riscv_gstage_vmid_detect(void); > +unsigned long kvm_riscv_gstage_vmid_bits(void); > +int kvm_riscv_gstage_vmid_init(struct kvm *kvm); > +bool kvm_riscv_gstage_vmid_ver_changed(struct kvm_vmid *vmid); > +void kvm_riscv_gstage_vmid_update(struct kvm_vcpu *vcpu); > +void kvm_riscv_gstage_vmid_sanitize(struct kvm_vcpu *vcpu); > + > +#endif > diff --git a/arch/riscv/kvm/aia_imsic.c b/arch/riscv/kvm/aia_imsic.c > index 29ef9c2133a9..40b469c0a01f 100644 > --- a/arch/riscv/kvm/aia_imsic.c > +++ b/arch/riscv/kvm/aia_imsic.c > @@ -16,6 +16,7 @@ > #include > #include > #include > +#include > > #define IMSIC_MAX_EIX (IMSIC_MAX_ID / BITS_PER_TYPE(u64)) > > diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c > index 4b24705dc63a..b861a5dd7bd9 100644 > --- a/arch/riscv/kvm/main.c > +++ b/arch/riscv/kvm/main.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > #include > #include > > diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c > index a5387927a1c1..c1a3eb076df3 100644 > --- a/arch/riscv/kvm/mmu.c > +++ b/arch/riscv/kvm/mmu.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include > #include > diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c > index f46a27658c2e..6fc4361c3d75 100644 > --- a/arch/riscv/kvm/tlb.c > +++ b/arch/riscv/kvm/tlb.c > @@ -15,6 +15,8 @@ > #include > #include > #include > +#include > +#include > > #define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) > > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > index 6eb11c913b13..8ad7b31f5939 100644 > --- a/arch/riscv/kvm/vcpu.c > +++ b/arch/riscv/kvm/vcpu.c > @@ -18,6 +18,7 @@ > #include > #include > #include > +#include > #include > #include > > diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c > index 85c43c83e3b9..965df528de90 100644 > --- a/arch/riscv/kvm/vcpu_exit.c > +++ b/arch/riscv/kvm/vcpu_exit.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > #include > > static int gstage_page_fault(struct kvm_vcpu *vcpu, struct kvm_run *run, > diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c > index b27ec8f96697..8601cf29e5f8 100644 > --- a/arch/riscv/kvm/vm.c > +++ b/arch/riscv/kvm/vm.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > > const struct _kvm_stats_desc kvm_vm_stats_desc[] = { > KVM_GENERIC_VM_STATS() > diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c > index 92c01255f86f..3b426c800480 100644 > --- a/arch/riscv/kvm/vmid.c > +++ b/arch/riscv/kvm/vmid.c > @@ -14,6 +14,8 @@ > #include > #include > #include > +#include > +#include > > static unsigned long vmid_version = 1; > static unsigned long vmid_next; LGTM. Reviewed-by: Atish Patra From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9F19C71157 for ; Wed, 18 Jun 2025 07:46:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=UyOhYcsuLpW5/e6ITQrw0c2NHTSc0+v40HJchp412vk=; b=NegI9GyNW2bnyV k7i2p1HCyWCQ18ZnOCldAaC4TI1qFHiYMgybH94e6Li/4t7ZeAjJK+l5uHt6ovs7f0F1SaxL43Ia8 oLGE6ytWSlJUPnzuogGw+SzX99hIhY5Kzbiq+e+1XuUri/z2eV+RWlKTL7wH+kDoAvHnVTxx0rdwX ca6UEqmz8UpHXprN2j7FxyYuT7sXJ4sqIVM7nNpJvRkzmoTiGWUpnehXVUBkofnGh49xYmHQX8WV1 TTmekcbzZ/ayYxxx2dXhEIhabp4lefjD1dmd9UxyPrI8/vUjIQMprChihn8M9lN3mOGEmGWcIA1af RhqmhmBDlZN7iuUGPi4Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uRnVK-00000009K53-2oQJ; Wed, 18 Jun 2025 07:46:42 +0000 Received: from out-174.mta1.migadu.com ([2001:41d0:203:375::ae]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uRmUA-00000009CbF-21YF for linux-riscv@lists.infradead.org; Wed, 18 Jun 2025 06:41:28 +0000 Message-ID: <8c51685c-de2f-48ed-b0b6-87ac44073684@linux.dev> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750228874; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Vx7JDHQ6srbDcbhQvBkA6hELvFYIhF9e9poQ0xOUOKU=; b=LSVfc6SsSY39VUCNHIgJHBxVAduEis1okaYmqlEta/beC6pWCMHiDXb8ENn+9cgxXfbWDc mq9E4uQsWEQGw70tjcMYaxay4likm+RkUbuzfA4s1apaPUs/SsGEgQXdps85zHQFD0W9DR iTs3i3xvcTYC+aiGX2yUt+C6iWk6Zfs= Date: Tue, 17 Jun 2025 23:41:08 -0700 MIME-Version: 1.0 Subject: Re: [PATCH v2 08/12] RISC-V: KVM: Factor-out MMU related declarations into separate headers To: Anup Patel Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250613065743.737102-1-apatel@ventanamicro.com> <20250613065743.737102-9-apatel@ventanamicro.com> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Atish Patra In-Reply-To: <20250613065743.737102-9-apatel@ventanamicro.com> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250617_234126_934154_6059E5F0 X-CRM114-Status: GOOD ( 18.68 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 6/12/25 11:57 PM, Anup Patel wrote: > The MMU, TLB, and VMID management for KVM RISC-V already exists as > seprate sources so create separate headers along these lines. This > further simplifies asm/kvm_host.h header. > > Signed-off-by: Anup Patel > --- > arch/riscv/include/asm/kvm_host.h | 100 +----------------------------- > arch/riscv/include/asm/kvm_mmu.h | 26 ++++++++ > arch/riscv/include/asm/kvm_tlb.h | 78 +++++++++++++++++++++++ > arch/riscv/include/asm/kvm_vmid.h | 27 ++++++++ > arch/riscv/kvm/aia_imsic.c | 1 + > arch/riscv/kvm/main.c | 1 + > arch/riscv/kvm/mmu.c | 1 + > arch/riscv/kvm/tlb.c | 2 + > arch/riscv/kvm/vcpu.c | 1 + > arch/riscv/kvm/vcpu_exit.c | 1 + > arch/riscv/kvm/vm.c | 1 + > arch/riscv/kvm/vmid.c | 2 + > 12 files changed, 143 insertions(+), 98 deletions(-) > create mode 100644 arch/riscv/include/asm/kvm_mmu.h > create mode 100644 arch/riscv/include/asm/kvm_tlb.h > create mode 100644 arch/riscv/include/asm/kvm_vmid.h > > diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h > index 6162575e2177..bd5341efa127 100644 > --- a/arch/riscv/include/asm/kvm_host.h > +++ b/arch/riscv/include/asm/kvm_host.h > @@ -16,6 +16,8 @@ > #include > #include > #include > +#include > +#include > #include > #include > #include > @@ -56,24 +58,6 @@ > BIT(IRQ_VS_TIMER) | \ > BIT(IRQ_VS_EXT)) > > -enum kvm_riscv_hfence_type { > - KVM_RISCV_HFENCE_UNKNOWN = 0, > - KVM_RISCV_HFENCE_GVMA_VMID_GPA, > - KVM_RISCV_HFENCE_VVMA_ASID_GVA, > - KVM_RISCV_HFENCE_VVMA_ASID_ALL, > - KVM_RISCV_HFENCE_VVMA_GVA, > -}; > - > -struct kvm_riscv_hfence { > - enum kvm_riscv_hfence_type type; > - unsigned long asid; > - unsigned long order; > - gpa_t addr; > - gpa_t size; > -}; > - > -#define KVM_RISCV_VCPU_MAX_HFENCE 64 > - > struct kvm_vm_stat { > struct kvm_vm_stat_generic generic; > }; > @@ -99,15 +83,6 @@ struct kvm_vcpu_stat { > struct kvm_arch_memory_slot { > }; > > -struct kvm_vmid { > - /* > - * Writes to vmid_version and vmid happen with vmid_lock held > - * whereas reads happen without any lock held. > - */ > - unsigned long vmid_version; > - unsigned long vmid; > -}; > - > struct kvm_arch { > /* G-stage vmid */ > struct kvm_vmid vmid; > @@ -311,77 +286,6 @@ static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) > return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; > } > > -#define KVM_RISCV_GSTAGE_TLB_MIN_ORDER 12 > - > -void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, > - gpa_t gpa, gpa_t gpsz, > - unsigned long order); > -void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid); > -void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz, > - unsigned long order); > -void kvm_riscv_local_hfence_gvma_all(void); > -void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid, > - unsigned long asid, > - unsigned long gva, > - unsigned long gvsz, > - unsigned long order); > -void kvm_riscv_local_hfence_vvma_asid_all(unsigned long vmid, > - unsigned long asid); > -void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid, > - unsigned long gva, unsigned long gvsz, > - unsigned long order); > -void kvm_riscv_local_hfence_vvma_all(unsigned long vmid); > - > -void kvm_riscv_tlb_flush_process(struct kvm_vcpu *vcpu); > - > -void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu); > -void kvm_riscv_hfence_vvma_all_process(struct kvm_vcpu *vcpu); > -void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu); > - > -void kvm_riscv_fence_i(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask); > -void kvm_riscv_hfence_gvma_vmid_gpa(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask, > - gpa_t gpa, gpa_t gpsz, > - unsigned long order); > -void kvm_riscv_hfence_gvma_vmid_all(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask); > -void kvm_riscv_hfence_vvma_asid_gva(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask, > - unsigned long gva, unsigned long gvsz, > - unsigned long order, unsigned long asid); > -void kvm_riscv_hfence_vvma_asid_all(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask, > - unsigned long asid); > -void kvm_riscv_hfence_vvma_gva(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask, > - unsigned long gva, unsigned long gvsz, > - unsigned long order); > -void kvm_riscv_hfence_vvma_all(struct kvm *kvm, > - unsigned long hbase, unsigned long hmask); > - > -int kvm_riscv_gstage_ioremap(struct kvm *kvm, gpa_t gpa, > - phys_addr_t hpa, unsigned long size, > - bool writable, bool in_atomic); > -void kvm_riscv_gstage_iounmap(struct kvm *kvm, gpa_t gpa, > - unsigned long size); > -int kvm_riscv_gstage_map(struct kvm_vcpu *vcpu, > - struct kvm_memory_slot *memslot, > - gpa_t gpa, unsigned long hva, bool is_write); > -int kvm_riscv_gstage_alloc_pgd(struct kvm *kvm); > -void kvm_riscv_gstage_free_pgd(struct kvm *kvm); > -void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu); > -void __init kvm_riscv_gstage_mode_detect(void); > -unsigned long __init kvm_riscv_gstage_mode(void); > -int kvm_riscv_gstage_gpa_bits(void); > - > -void __init kvm_riscv_gstage_vmid_detect(void); > -unsigned long kvm_riscv_gstage_vmid_bits(void); > -int kvm_riscv_gstage_vmid_init(struct kvm *kvm); > -bool kvm_riscv_gstage_vmid_ver_changed(struct kvm_vmid *vmid); > -void kvm_riscv_gstage_vmid_update(struct kvm_vcpu *vcpu); > -void kvm_riscv_gstage_vmid_sanitize(struct kvm_vcpu *vcpu); > - > int kvm_riscv_setup_default_irq_routing(struct kvm *kvm, u32 lines); > > void __kvm_riscv_unpriv_trap(void); > diff --git a/arch/riscv/include/asm/kvm_mmu.h b/arch/riscv/include/asm/kvm_mmu.h > new file mode 100644 > index 000000000000..4e1654282ee4 > --- /dev/null > +++ b/arch/riscv/include/asm/kvm_mmu.h > @@ -0,0 +1,26 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2025 Ventana Micro Systems Inc. > + */ > + > +#ifndef __RISCV_KVM_MMU_H_ > +#define __RISCV_KVM_MMU_H_ > + > +#include > + > +int kvm_riscv_gstage_ioremap(struct kvm *kvm, gpa_t gpa, > + phys_addr_t hpa, unsigned long size, > + bool writable, bool in_atomic); > +void kvm_riscv_gstage_iounmap(struct kvm *kvm, gpa_t gpa, > + unsigned long size); > +int kvm_riscv_gstage_map(struct kvm_vcpu *vcpu, > + struct kvm_memory_slot *memslot, > + gpa_t gpa, unsigned long hva, bool is_write); > +int kvm_riscv_gstage_alloc_pgd(struct kvm *kvm); > +void kvm_riscv_gstage_free_pgd(struct kvm *kvm); > +void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu); > +void kvm_riscv_gstage_mode_detect(void); > +unsigned long kvm_riscv_gstage_mode(void); > +int kvm_riscv_gstage_gpa_bits(void); > + > +#endif > diff --git a/arch/riscv/include/asm/kvm_tlb.h b/arch/riscv/include/asm/kvm_tlb.h > new file mode 100644 > index 000000000000..cd00c9a46cb1 > --- /dev/null > +++ b/arch/riscv/include/asm/kvm_tlb.h > @@ -0,0 +1,78 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2025 Ventana Micro Systems Inc. > + */ > + > +#ifndef __RISCV_KVM_TLB_H_ > +#define __RISCV_KVM_TLB_H_ > + > +#include > + > +enum kvm_riscv_hfence_type { > + KVM_RISCV_HFENCE_UNKNOWN = 0, > + KVM_RISCV_HFENCE_GVMA_VMID_GPA, > + KVM_RISCV_HFENCE_VVMA_ASID_GVA, > + KVM_RISCV_HFENCE_VVMA_ASID_ALL, > + KVM_RISCV_HFENCE_VVMA_GVA, > +}; > + > +struct kvm_riscv_hfence { > + enum kvm_riscv_hfence_type type; > + unsigned long asid; > + unsigned long order; > + gpa_t addr; > + gpa_t size; > +}; > + > +#define KVM_RISCV_VCPU_MAX_HFENCE 64 > + > +#define KVM_RISCV_GSTAGE_TLB_MIN_ORDER 12 > + > +void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, > + gpa_t gpa, gpa_t gpsz, > + unsigned long order); > +void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid); > +void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz, > + unsigned long order); > +void kvm_riscv_local_hfence_gvma_all(void); > +void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid, > + unsigned long asid, > + unsigned long gva, > + unsigned long gvsz, > + unsigned long order); > +void kvm_riscv_local_hfence_vvma_asid_all(unsigned long vmid, > + unsigned long asid); > +void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid, > + unsigned long gva, unsigned long gvsz, > + unsigned long order); > +void kvm_riscv_local_hfence_vvma_all(unsigned long vmid); > + > +void kvm_riscv_tlb_flush_process(struct kvm_vcpu *vcpu); > + > +void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu); > +void kvm_riscv_hfence_vvma_all_process(struct kvm_vcpu *vcpu); > +void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu); > + > +void kvm_riscv_fence_i(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask); > +void kvm_riscv_hfence_gvma_vmid_gpa(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask, > + gpa_t gpa, gpa_t gpsz, > + unsigned long order); > +void kvm_riscv_hfence_gvma_vmid_all(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask); > +void kvm_riscv_hfence_vvma_asid_gva(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask, > + unsigned long gva, unsigned long gvsz, > + unsigned long order, unsigned long asid); > +void kvm_riscv_hfence_vvma_asid_all(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask, > + unsigned long asid); > +void kvm_riscv_hfence_vvma_gva(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask, > + unsigned long gva, unsigned long gvsz, > + unsigned long order); > +void kvm_riscv_hfence_vvma_all(struct kvm *kvm, > + unsigned long hbase, unsigned long hmask); > + > +#endif > diff --git a/arch/riscv/include/asm/kvm_vmid.h b/arch/riscv/include/asm/kvm_vmid.h > new file mode 100644 > index 000000000000..ab98e1434fb7 > --- /dev/null > +++ b/arch/riscv/include/asm/kvm_vmid.h > @@ -0,0 +1,27 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2025 Ventana Micro Systems Inc. > + */ > + > +#ifndef __RISCV_KVM_VMID_H_ > +#define __RISCV_KVM_VMID_H_ > + > +#include > + > +struct kvm_vmid { > + /* > + * Writes to vmid_version and vmid happen with vmid_lock held > + * whereas reads happen without any lock held. > + */ > + unsigned long vmid_version; > + unsigned long vmid; > +}; > + > +void __init kvm_riscv_gstage_vmid_detect(void); > +unsigned long kvm_riscv_gstage_vmid_bits(void); > +int kvm_riscv_gstage_vmid_init(struct kvm *kvm); > +bool kvm_riscv_gstage_vmid_ver_changed(struct kvm_vmid *vmid); > +void kvm_riscv_gstage_vmid_update(struct kvm_vcpu *vcpu); > +void kvm_riscv_gstage_vmid_sanitize(struct kvm_vcpu *vcpu); > + > +#endif > diff --git a/arch/riscv/kvm/aia_imsic.c b/arch/riscv/kvm/aia_imsic.c > index 29ef9c2133a9..40b469c0a01f 100644 > --- a/arch/riscv/kvm/aia_imsic.c > +++ b/arch/riscv/kvm/aia_imsic.c > @@ -16,6 +16,7 @@ > #include > #include > #include > +#include > > #define IMSIC_MAX_EIX (IMSIC_MAX_ID / BITS_PER_TYPE(u64)) > > diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c > index 4b24705dc63a..b861a5dd7bd9 100644 > --- a/arch/riscv/kvm/main.c > +++ b/arch/riscv/kvm/main.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > #include > #include > > diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c > index a5387927a1c1..c1a3eb076df3 100644 > --- a/arch/riscv/kvm/mmu.c > +++ b/arch/riscv/kvm/mmu.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include > #include > diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c > index f46a27658c2e..6fc4361c3d75 100644 > --- a/arch/riscv/kvm/tlb.c > +++ b/arch/riscv/kvm/tlb.c > @@ -15,6 +15,8 @@ > #include > #include > #include > +#include > +#include > > #define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) > > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > index 6eb11c913b13..8ad7b31f5939 100644 > --- a/arch/riscv/kvm/vcpu.c > +++ b/arch/riscv/kvm/vcpu.c > @@ -18,6 +18,7 @@ > #include > #include > #include > +#include > #include > #include > > diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c > index 85c43c83e3b9..965df528de90 100644 > --- a/arch/riscv/kvm/vcpu_exit.c > +++ b/arch/riscv/kvm/vcpu_exit.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > #include > > static int gstage_page_fault(struct kvm_vcpu *vcpu, struct kvm_run *run, > diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c > index b27ec8f96697..8601cf29e5f8 100644 > --- a/arch/riscv/kvm/vm.c > +++ b/arch/riscv/kvm/vm.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > > const struct _kvm_stats_desc kvm_vm_stats_desc[] = { > KVM_GENERIC_VM_STATS() > diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c > index 92c01255f86f..3b426c800480 100644 > --- a/arch/riscv/kvm/vmid.c > +++ b/arch/riscv/kvm/vmid.c > @@ -14,6 +14,8 @@ > #include > #include > #include > +#include > +#include > > static unsigned long vmid_version = 1; > static unsigned long vmid_next; LGTM. Reviewed-by: Atish Patra _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv