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Mon, 22 Sep 2025 16:57:12 -0700 (PDT) Received: from [192.168.0.13] ([172.92.174.155]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77e0bb98790sm11669657b3a.9.2025.09.22.16.57.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Sep 2025 16:57:11 -0700 (PDT) Message-ID: <8ca8192e-ccc1-41bb-a913-dd633d65ac54@gmail.com> Date: Mon, 22 Sep 2025 16:55:57 -0700 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 00/11] riscv: Memory type control for platforms with physical memory aliases To: Samuel Holland , Palmer Dabbelt , linux-riscv@lists.infradead.org, Conor Dooley Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandre Ghiti , Lad Prabhakar , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , uwu@icenowy.me References: <20241102000843.1301099-1-samuel.holland@sifive.com> Content-Language: en-US From: Bo Gan In-Reply-To: <20241102000843.1301099-1-samuel.holland@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/1/24 17:07, Samuel Holland wrote: > > On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700, > RAM is mapped to multiple physical address ranges, with each alias > having a different set of statically-determined Physical Memory > Attributes (PMAs). Software selects the PMAs for a page by choosing a > PFN from the corresponding physical address range. On these platforms, > this is the only way to allocate noncached memory for use with > noncoherent DMA. > > - Patch 1 adds a new binding to describe physical memory regions in > the devicetree. > - Patches 2-6 refactor existing memory type support to be modeled as > variants on top of Svpbmt. > - Patches 7-10 add logic to transform the PFN to use the desired alias > when reading/writing page tables. > - Patch 11 enables this new method of memory type control on JH7100. > > I have boot-tested this series on platforms with each of the 4 ways to > select a memory type: SiFive FU740 (none), QEMU (Svpbmt), Allwinner D1 > (XTheadMae), and ESWIN EIC7700 (aliases). > Hi Samuel, Any update on this? I see ESWIN has started their EIC7700 upstreaming effort, and it'll likely rely on this. Is there any follow up series? BTW, Icenowy's working on upstreaming the Verisilicon DC8200 driver. His work also depend on this patchset in order to test on JH7110/EIC7700 Thanks! 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Mon, 22 Sep 2025 16:57:12 -0700 (PDT) Received: from [192.168.0.13] ([172.92.174.155]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77e0bb98790sm11669657b3a.9.2025.09.22.16.57.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Sep 2025 16:57:11 -0700 (PDT) Message-ID: <8ca8192e-ccc1-41bb-a913-dd633d65ac54@gmail.com> Date: Mon, 22 Sep 2025 16:55:57 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 00/11] riscv: Memory type control for platforms with physical memory aliases To: Samuel Holland , Palmer Dabbelt , linux-riscv@lists.infradead.org, Conor Dooley References: <20241102000843.1301099-1-samuel.holland@sifive.com> Content-Language: en-US From: Bo Gan In-Reply-To: <20241102000843.1301099-1-samuel.holland@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250922_165713_932072_6A3CD9D4 X-CRM114-Status: GOOD ( 15.96 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Emil Renner Berthing , Lad Prabhakar , linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Alexandre Ghiti Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 11/1/24 17:07, Samuel Holland wrote: > > On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700, > RAM is mapped to multiple physical address ranges, with each alias > having a different set of statically-determined Physical Memory > Attributes (PMAs). Software selects the PMAs for a page by choosing a > PFN from the corresponding physical address range. On these platforms, > this is the only way to allocate noncached memory for use with > noncoherent DMA. > > - Patch 1 adds a new binding to describe physical memory regions in > the devicetree. > - Patches 2-6 refactor existing memory type support to be modeled as > variants on top of Svpbmt. > - Patches 7-10 add logic to transform the PFN to use the desired alias > when reading/writing page tables. > - Patch 11 enables this new method of memory type control on JH7100. > > I have boot-tested this series on platforms with each of the 4 ways to > select a memory type: SiFive FU740 (none), QEMU (Svpbmt), Allwinner D1 > (XTheadMae), and ESWIN EIC7700 (aliases). > Hi Samuel, Any update on this? I see ESWIN has started their EIC7700 upstreaming effort, and it'll likely rely on this. Is there any follow up series? BTW, Icenowy's working on upstreaming the Verisilicon DC8200 driver. His work also depend on this patchset in order to test on JH7110/EIC7700 Thanks! _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv