Re: [PATCH v2 1/3] KVM: x86: Deflect unknown MSR accesses to user space

[Alexander Graf <graf@amazon.com>]

On 31.07.20 05:20, Jim Mattson wrote:
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> On Thu, Jul 30, 2020 at 4:53 PM Jim Mattson <jmattson@google.com> wrote:
>>
>> On Thu, Jul 30, 2020 at 4:08 PM Alexander Graf <graf@amazon.com> wrote:
>>> Do you have a particular situation in mind where that would not be the
>>> case and where we would still want to actually complete an MSR operation
>>> after the environment changed?
>>
>> As far as userspace is concerned, if it has replied with error=0, the
>> instruction has completed and retired. If the kernel executes a
>> different instruction at CS:RIP, the state is certainly inconsistent
>> for WRMSR exits. It would also be inconsistent for RDMSR exits if the
>> RDMSR emulation on the userspace side had any side-effects.
> 
> Actually, I think there's a potential problem with interrupt delivery
> even if the instruction bytes are the same. On the second pass, an
> interrupt could be delivered on the CS:IP of a WRMSR, even though
> userspace has already emulated the WRMSR instruction. This could be
> particularly awkward if the WRMSR was to the x2APIC TPR register, and
> in fact lowered the TPR sufficiently to allow a pending interrupt to
> be delivered.

Ok, you got me convinced here :). The following flow breaks with my model:

   * rdmsr on 0x123, traps to user space
   * user space handles it, writes data into run->msr
   * kernel injects pending IRQ
   * IRQ handler does rdmsr on 0x124, which would be handled by user space
   * kernel returns value for 0x123 to the read

So yes, I agree, we have to finish the instruction handling before we 
can go back into normal operation flow.


Alex



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